Z8PE002 Datasheet, PDF (19/48 Pages) Zilog, Inc. – FEATURE-ENHANCED Z8PLUS 0.5K ROM ONE-TIME PROGRAMMABLE(OTP) MICROCONTROLLER

ZiLOG
Table 11. Interrupt Mask Register—IMASK (FBh)
Bit
7 65 4 3 2 1 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
R = Read W = Write X = Indeterminate U = Undefined/
Undetermined
Bit
Position
7
R/W
6
5
4
3
2
1
0
Value
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
Description
Disables Interrupts
Enables Interrupts
Reserved, must be 0
Disables IRQ5
Enables IRQ5
Disables IRQ4
Enables IRQ4
Disables IRQ3
Enables IRQ3
Disables IRQ2
Enables IRQ2
Disables IRQ1
Enables IRQ1
Disables IRQ0
Enables IRQ0
Z8PE002
Z8Plus OTP Microcontroller
Interrupt Request (IREQ) Register Initialization
IREQ (Table 12) is a register that stores the interrupt re-
quests for both vectored and polled interrupts. When an in-
terrupt is issued, the corresponding bit position in the reg-
ister is set to 1. Bits 0 to 5 are assigned to interrupt requests
IREQ0 to IREQ5, respectively.
Whenever RESET is executed, the IREQ resistor is set to
00h.
Table 12. Interrupt Request Register–IREQ (FAh)
Bit
R/W
Reset
7 65 4 3 2 1 0
R/W R/W R/W R/W R/W R/W R/W R/W
0 00 0 0 0 0 0
R = Read W = Write X = Indeterminate U = Undefined/
Undetermined
Bit
Position
7
6
5
R/W
R/W
R/W
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
R/W
Value
0
0
0
1
0
1
0
1
0
1
0
1
0
1
Description
Reserved, must be 0
Reserved, must be 0
IRQ5 reset
IRQ5 set
IRQ4 reset
IRQ4 set
IRQ3 reset
IRQ3 set
IRQ2 reset
IRQ2 set
IRQ1 reset
IRQ1 set
IRQ0 reset
IRQ0 set
DS008700-Z8X0799
PRELIMINARY
19