Z8F64200100KITG Datasheet, PDF (16/18 Pages) Zilog, Inc. – Z8 Encore! XP Z8F642 Development Board

Z8 Encore! XP^® F64XX Series Development Kit
User Manual
13
5
4
3
PA2
PA1_T0OUT
2
1
connector 2
JP2
L1
C11
C12
C13
C14
PE7
1
2
PE6
PE5
3
4
PE4
VCC_33V
D
VCC_33V 1 _IO
IO ³
AVDD
EMI Filter
0.001uF
0.1uF
0.1uF
0.001uF
DBG
PA5_TXD0
PA3_CTS0
PA4_RXD0
DBG
PA5_TXD0
PA3_CTS0
PA4_RXD0
PE3
5
6
PE2
PE1
7
8
PE0
VCC_33V
9
10
GND
PC4_MOSI
11
12
PC5_MISO
PC7_T2OUT
13
14
PC6_T2IN
PC3_SCK
15
16
PC2_SS
D
PC0_T1IN
17
18
PA0_T0IN
GND
19
20
PA1_T0OUT
U6
PC1_T1OUT
21
22
PA2
GND
GND
AGND
PD1_T3OUT
23
PD3
25
24
PD6_CTS1
26
PD4_RXD1
PD5_TXD1
27
28
PD0_T3IN
PD7_RCOUT
29
PF0
31
30
GND
32
PD2
PA3_CTS0
33
34
PG0
PA4_RXD0
35
36
PA5_TXD0
JP13
1
C
Header 1
JP14
1
Header 1
JP6
1
Header 1
JP7
1
SW2
PF7
PF6
PF5
PF4
RESET
-RESET
PA0_T0IN
C15
0.001uF
C16
0.1uF
C19
0.001uF
C20
0.1uF
R12
220
PA0_T0IN
PD2
PC2_SS
PF6
VCC_33V
PF5
PF4
PF3
PE4
PE3
GND
PE2
PE1
PE0
GND
PF2
PF1
PF0
VCC_33V
PD1_T3OUT
PD0_T3IN
XOUT
XIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PA0/T0IN
PD2
PC2/SS
PF6
RESET
VDD
PF5
PF4
PF3
PE4
PE3
GND
PE2
PE1
PE0
GND
PF2
PF1
PF0
VDD
PD1/T3OUT
PD0/T3IN
XOUT
XIN
PA7/SDA
PD6/CTS1
PC3/SCK
PD7/RCOUT
PG0
GND
PG1
PG2
PE5
PE6
PE7
VDD
PG3
PG4
PG5
PG6
VDD
PG7
PC7/T2OUT
PC6/T2IN
DBG
PC1/T1OUT
PC0/T1IN
GND
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PA7_SDA
PD6_CTS1
PC3_SCK
PD7_RCOUT
PG0
GND
PG1
PG2
PE5
PE6
PE7
VCC_33V
PG3
PG4
PG5
PG6
VCC_33V
PG7
PC7_T2OUT
PC6_T2IN
DBG
PC1_T1OUT
PC0_T1IN
GND
PG1
PG2
C17
0.1uF
C18
0.001uF
PG3
PG4
C21
C22
0.1uF
0.001uF
PG5
PC0_T1IN
PG6
JP15
1
Header 1
JP16
1
Header 1
JP17
1
Header 1
JP18
1
Header 1
JP19
1
Header 1
JP20
1
GND ^NC
37
39
NC 41
PA6_SCL ^NC
43
45
PA7_SDA
47
NC 49
-RESET
NC ⁵¹
53
VCC_33V
55
VCC_33V ^NC
57
59
38 NC
40 NC
42 NC
44 NC
46
48
GND
50
52 -DIS_IrDA
54 NC
56
GND
-DIS_232
-DIS_IRDA
58 NC
60 NC
C
HEADER 30x2/SM
If Module is plugged onto the Dev Platform the local
RS232 interface is disabled by pin 50 of JP2
JP1
1
2
Y1
Header 1
Header 1
3
4
-TRSTN
5
6
JP8
PF3
1
Header 1
JP9
B
1
PF2
Header 1
JP10
PF1
1
Header 1
18.432MHz
R13 100K
C23
18pF
18pF
C24
Z8F642
JP21
-F91_WE 7
PG7
1
GND
9
A6
11
A10
13
Header 1
GND
15
A8
17
A13
19
connector 1
A15
21
A18
23
for
A19
25
A2
27
reference
A11
29
A4
31
only
A5
33
35
A21
37
8
10
12
VCC_33V
A0
VCC_33V
14 A3
16
VCC_33V
18 A7
20 A9
B
22 A14
24 A16
26
GND
28
A1
30
A12
32
A20
34 A17
36 ^-DIS_FLASH
38
VCC_33V
PH0_ANA8
PH1_ANA9
PB0_ANA0
PB1_ANA1
PB4_ANA4 PB5_ANA5
PB6_ANA6 PB7_ANA7
PB3_ANA3
PB2_ANA2 PH2_ANA10 PH3_ANA11
A22
39
-CS0
41
40 A23
42 -CS1
-CS2
43
44 D0
+ C25
D1
45
46 D2
C26
0.001uF
C27
0.001uF
C28
0.001uF
C29
0.001uF
C30
0.001uF
C31
0.001uF
C32
0.001uF
C33
0.001uF
C34
0.001uF
C35
0.001uF
C36
0.001uF
C37
0.001uF
22uF
C38
0.01uF
D3
47
D5
49
48 D4
50 GND
AGND
D7
51
-MREQ 53
52 D6
54 -IOREQ
J2
GND
55
-WR 57
56 -RD
58 -INSTRD
PH0_ANA8
PH1_ANA9
PB0_ANA0
PB1_ANA1
25
26
23
24
21
22
A
PB4_ANA4
PB5_ANA5
PB6_ANA6
PB7_ANA7
PB3_ANA3
19
20
17
18
15
16
13
14
11
12
PB2_ANA2
PH2_ANA10
PH3_ANA11
9
7
5
10
8
6
VREF
3
4
1
2
-BUSACK 59
60 -BUSREQ
HEADER 30x2/SM
A
Title
Encore! F642. Evaluation Module. Schematic.
Size Document Number
Rev
B
96C0918-001
A
Date:
Friday, June 06, 2003
Sheet
2
of 2
5
4
3
2
1
Schematics
Figure 4. Z8 Encore! XP F64XX Series Development Board (Continued)
UM015110-0508