EZ80F915005MOD Datasheet, PDF (11/25 Pages) Zilog, Inc. – eZ80F91 Mini Enet Module

eZ80F915005MOD
eZ80F91 Mini Enet Module Product Specification
6
Table 1. eZ80Acclaim! Development Platform
Peripheral Bus Connector J1 Identification^1,2 (Continued)
Pin # Symbol Signal Direction Active Level eZ80F91 Signal
Note
27 A23
Bidirectional
n/a
Yes
28 CS0
Output
Low
Yes
29 CS3
Output
Low
Yes
33 F91_WE Input
Low
No
Jumper on board
34 CS0
Output
Low
Yes
35 D3
Bidirectional
n/a
Yes
36 RTC_V_DD Input
n/a
Yes
39 D7
Bidirectional
n/a
Yes
40 HALT_SLP Output
Low
Yes
41 A13
Bidirectional
n/a
Yes
42 WR
Ouput
Low
Yes
43 A12
Bidirectional
n/a
Yes
44 A11
Bidirectional
n/a
Yes
45 A14
Bidirectional
n/a
Yes
46 A9
Bidirectional
n/a
Yes
49 A16
Bidirectional
n/a
Yes
50 A5
Bidirectional
n/a
Yes
51 A15
Bidirectional
n/a
Yes
52 A4
Bidirectional
n/a
Yes
Notes:
1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from
this table. The entire interface is represented in the eZ80F91 Mini Enet Module schematics on
pages 31 through 32.
2. Additional note: external capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23
should be below 10 pF to satisfy the timing requirements for the eZ80^® CPU. All unused inputs
should be pulled to either V_DD or GND, depending on their inactive levels to reduce power
consumption and to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be
deactivated via software in the eZ80F91’s Peripheral Power-Down Register.
PS023602-0804
PRELIMINARY
Pin Description