Z89390 Datasheet, PDF (10/11 Pages) Zilog, Inc. – 16-BIT DIGITAL SIGNAL PROCESSOR

ZILOG
AC TIMING (Continued)
CLOCK
/RESET
INTERNAL
RESET
EXECUTE
TCY
RSET
RWIDTH
Cycle 0
Cycle 1
RD/WR
/DS
UO0-1
EA0-2
EXT0-15
PA0-15
RAM/
REGISTERS
PRELIMINARY
Z89390
CPS DC-9030-01
RRISE
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Code Execution
Tri-Stated
Tri-Stated
Access Reset Vector
Intact*
RESET Timing Diagram
* The RAM and hardware registers are left intact
during a warm reset. A cold reset will produce
random data in these locations. The status
register is set to zeroes in both cases.
CLOCK
PROGRAM
ADDRESS
PROGRAM
DATA
TCY
PASET
Valid
PDSET
Valid
Valid
PDHOLD
Valid
External Memory Port Timing Diagram
Valid
Valid
10
DC 9030-00