Z86E3116SSG Datasheet, PDF (1/64 Pages) Zilog, Inc. – Z8 4K OTP MICROCONTROLLER

PRELIMINARY PRODUCT SPECIFICATION
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Z86E30/E31/E40
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Z8 4K OTP MICROCONTROLLER
FEATURES
Device
ROM
(KB)
Z86E30
4
Z86E31
2
Z86E40
4
Note: *General-Purpose
RAM*
(Bytes)
237
125
236
I/O
Lines
24
24
32
Speed
(MHz)
16
16
16
s Standard Temperature (V_CC = 3.5V to 5.5V)
s Extended Temperature (V_CC = 4.5V to 5.5V)
s Available Packages:
28-Pin DIP/SOIC/PLCC OTP (Z86E30/31 only)
40-Pin DIP OTP (Z86E40 only)
44-Pin P^PL^LC^CC^C/^/Q^LQFP^FPOT^OP^TP(Z⁽8^Z6⁸E⁶4^E0⁴o⁰n^olyⁿ)^ly)
s Software Enabled Watch-Dog Timer (WDT)
s Push-Pull/Open-Drain Programmable on
Port 0, Port 1, and Port 2
s 24/32 Input/Output Lines
s Auto Latches
s Auto Power-On Reset (POR)
s Programmable OTP Options:
RC Oscillator
EPROM Protect
Auto Latch Disable
Permanently Enabled WDT
Crystal Oscillator Feedback Resistor Disable
RAM Protect
s Low-Power Consumption: 60 mW
s Fast Instruction Pointer: 0.75 µs
s Two Standby Modes: STOP and HALT
s Digital Inputs CMOS Levels, Schmitt-Triggered
s Software Programmable Low EMI Mode
s Two Programmable 8-Bit Counter/Timers Each
with a 6-Bit Programmable Prescaler
s Six Vectored, Priority Interrupts from Six
Different Sources
s Two Comparators
s On-Chip Oscillator that Accepts a Crystal, Ceramic
Resonator, LC, RC, or External Clock Drive
GENERAL DESCRIPTION
The Z86E30/E31/E40 8-Bit One-Time Programmable
(OTP) Microcontrollers are members of Zilog's single-chip
Z8^® MCU family featuring enhanced wake-up circuitry,
programmable Watch-Dog Timers, Low Noise EMI op-
tions, and easy hardware/software system expansion ca-
pability.
Four basic address spaces support a wide range of mem-
ory configurations. The designer has access to three addi-
tional control registers that allow easy access to register
mapped peripheral and I/O circuits.
For applications demanding powerful I/O capabilities, the
Z86E30/E31 have 24 pins, and the Z86E40 has 32 pins of
dedicated input and output. These lines are grouped into
four ports, eight lines per port, and are configurable under
software control to provide timing, status signals, and par-
allel I/O with or without handshake, and address/data bus
for interfacing external memory.
Notes: All signals with a preceding front slash, “/”, are
active Low. For example, B/W (WORD is active Low); B/W
(BYTE is active Low, only).
DS97Z8X0502
PRELIMINARY
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