SCT1555 Datasheet, PDF (7/10 Pages) Zetex Semiconductors – PRECISION SINGLE CELL TIMER

ZSCT1555
APPLICATIONS INFORMATION
Many configurations of the ZSCT1555 are
possible. The following gives a selection of a
few of these using the most basic monostable
and astable connections. The final application
example in astable mode shows the device
optimum use for low voltage and power
economy in a single cell boost converter.
Monostable Operation
Figure 1 shows connection of the timer as a
one-shot whose pulse period is independent
of supply voltage. Initially the capacitor is held
discharged. The application of a negative
going trigger pulse sets an internal flip flop
which allows the capacitor to start to charge
up via RA and forces the output high. The
voltage on the capacitor increases for time t,
where t = 1.63RAC_T, at the end of this period
the voltage on the capacitor is 0.8 V_CC. At this
point the flip flop resets, the capacitor is
discharged and the output is driven low.
Figure 2
Figure 3 gives an easy selection of RA and C_T
values for various time delays.
100
RA
10
1
0.1
100k
1M
10M
0.01
0.001
10us 100us 1ms 10ms 100ms 1s 10s
Figure 3
Time Delay
Figure 1
This configuration of circuit can be used as a
frequency divider by adjusting the timing
period. Figure 4 indicates a divide by three.
Figure 2 shows the timing diagram for this
function. During the output high period
further trigger pulses are locked out however
the circuit can be reset by application of a
negative going pulse on the reset pin. Once
the output is driven low it remains in this state
until the application of the next trigger pulse.
If the reset function is not used then it is
recommended to connect to V_CC to eliminate
any possibility of false triggering.
Figure 4
4-317