ZXCW8100S28 Datasheet, PDF (12/21 Pages) Zetex Semiconductors – 32 BIT STEREO DIRECT DRIVE DIGITAL AUDIO AMPLIFIER

ZXCW8100S28
PIN FUNCTIONAL DESCRIPTIONS
SPI interface
Pins SPI-EN, SPI-DA, SPI-CK form the SPI interface. The
enable, SPI-EN, is active low. Data is transmitted on
SPI-DA as a 72 bit word, there are 8 control bits and 64
data bits, SPI-CK provides the clock for the SPI
interface. The function of the control and data bits is
detailed in the Register Description section. The SPI
interface is also bi-directional with the read/write
function set in the first 8 control bits.
In write mode (figure 1) a full 72 bits is sent from the
host controller consisting of the 8 preamble control bits
with the R/W bit set low and the 64 SPI data bits. The
SPI-EN signal must be held low, enabled, for all 72
clocks and data bits as a validity check is run on the
incoming data string and any string not 72 bit long is
rejected. It is recommended to perform a read back of
the SPI data registers to validate the receipt of the
correct instruction.
In read mode (figure 2) the host controller sends the
first 8 preamble control bits with the R/W bit set high.
The SPI-DA pin of the ZXCW8100 device changes state
from being an input to being an output on the falling
edge following the R/W bit. The device then reads out
the data from the internal SPI register onto the SPI-DA
wire.
Data can be sent to SPI interface using two methods -
burst mode or continuos mode. In burst mode data will
be sent as a single 72 bit SPI data word accompanied by
72 SPI-CK clock bits. This data would be sent as and
when operating parameters are required to be
changed.
In continuous mode the SPI-CK clock will run
continuously with the SPI-DA data being resent
regardless of whether operating parameters are
required to be changed or not. The only requirement
for this mode, or for burst mode, as regard the
frequency of SPI update is that the SPI-EN enable line is
returned high for a minimum of 3 M-CK master clock
cycles between SPI data words.
The SPI interface can operate asynchronously to the
M-CK master clock and to any other data inputs. It can
run up to a maximum of 40 MHz however, it is expected
that one eighth the M-CK clock frequency would be
normal for most requirements.
Chip select
The hard wiring of the chip address is achieved with
pins CSL0 and CSL1. These are chosen to match the
code set in the first two bits of the 8 control bits of the
SPI word.
SPI Interface - Write Mode (figure 1)
SPI Interface - Read Mode (figure 2)
ISSUE 1 - JULY 2002
12