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ZVP2120A Datasheet, PDF (1/3 Pages) Zetex Semiconductors – P-CHANNEL ENHANCEMENT MODE VERTICAL DMOS FET
P-CHANNEL ENHANCEMENT
MODE VERTICAL DMOS FET
ISSUE 2 – MARCH 94
FEATURES
* 200 Volt VDS
* RDS(on)=25Ω
ZVP2120A
ABSOLUTE MAXIMUM RATINGS.
PARAMETER
Drain-Source Voltage
Continuous Drain Current at Tamb=25°C
Pulsed Drain Current
Gate Source Voltage
Power Dissipation at Tamb=25°C
Operating and Storage Temperature Range
SYMBOL
VDS
ID
IDM
VGS
Ptot
Tj:Tstg
DG
S
E-Line
TO92 Compatible
VALUE
-200
-120
-1.2
± 20
700
-55 to +150
UNIT
V
mA
A
V
mW
°C
ELECTRICAL CHARACTERISTICS (at Tamb = 25°C unless otherwise stated).
PARAMETER
SYMBOL MIN. MAX. UNIT CONDITIONS.
Drain-Source Breakdown
Voltage
BVDSS -200
V
ID=-1mA, VGS=0V
Gate-Source Threshold
Voltage
VGS(th) -1.5 -3.5 V
ID=-1mA, VDS= VGS
Gate-Body Leakage
IGSS
Zero Gate Voltage Drain
IDSS
Current
20 nA
-10 µA
-100 µA
VGS=± 20V, VDS=0V
VDS=-200 V, VGS=0
VDS=-160 V, VGS=0V,
T=125°C(2)
On-State Drain Current(1)
Static Drain-Source
On-State Resistance (1)
ID(on)
RDS(on)
-300
25
mA VDS=-25 V, VGS=-10V
Ω
VGS=-10V,ID=-150mA
Forward Transconductance gfs
50
(1)(2)
mS VDS=-25V,ID=-150mA
Input Capacitance (2)
Ciss
Common Source Output
Coss
Capacitance (2)
100 pF
25 pF
VDS=-25V, VGS=0V, f=1MHz
Reverse Transfer
Crss
7
pF
Capacitance (2)
Turn-On Delay Time (2)(3)
Rise Time (2)(3)
Turn-Off Delay Time (2)(3)
Fall Time (2)(3)
td(on)
tr
td(off)
tf
7
ns
15
ns
VDD≈-25V, ID=-150mA
12 ns
15 ns
(1) Measured under pulsed conditions. Width=300µs. Duty cycle ≤2%
(2) Sample test.
3-425
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