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ZVP2110A Datasheet, PDF (1/3 Pages) Zetex Semiconductors – P-CHANNEL ENHANCEMENT MODE VERTICAL DMOS FET
P-CHANNEL ENHANCEMENT
MODE VERTICAL DMOS FET
ISSUE 2 – MARCH 94
FEATURES
* 100 Volt VDS
* RDS(on)=8Ω
ZVP2110A
ABSOLUTE MAXIMUM RATINGS.
PARAMETER
Drain-Source Voltage
Continuous Drain Current at Tamb=25°C
Pulsed Drain Current
Gate Source Voltage
Power Dissipation at Tamb=25°C
Operating and Storage Temperature Range
SYMBOL
VDS
ID
IDM
VGS
Ptot
Tj:Tstg
D
G
S
E-Line
TO92 Compatible
VALUE
-100
-230
-3
± 20
700
-55 to +150
UNIT
V
mA
A
V
mW
°C
ELECTRICAL CHARACTERISTICS (at Tamb = 25°C unless otherwise stated).
PARAMETER
SYMBOL MIN. MAX. UNIT CONDITIONS.
Drain-Source Breakdown
Voltage
BVDSS -100
V
ID=-1mA, VGS=0V
Gate-Source Threshold
Voltage
VGS(th) -1.5 -3.5 V
ID=-1mA, VDS= VGS
Gate-Body Leakage
Zero Gate Voltage Drain
Current
IGSS
IDSS
On-State Drain Current(1)
ID(on)
Static Drain-Source On-State RDS(on)
Resistance (1)
20 nA
-1
µA
-100 µA
-750
mA
8
Ω
VGS=± 20V, VDS=0V
VDS=-100 V, VGS=0
VDS=-80 V, VGS=0V, T=125°C(2)
VDS=-25 V, VGS=-10V
VGS=-10V,ID=-375mA
Forward Transconductance gfs
125
(1)(2)
mS VDS=-25V,ID=-375mA
Input Capacitance (2)
Common Source Output
Capacitance (2)
Ciss
Coss
100 pF
35 pF
VDS=-25V, VGS=0V, f=1MHz
Reverse Transfer
Crss
10 pF
Capacitance (2)
Turn-On Delay Time (2)(3)
Rise Time (2)(3)
Turn-Off Delay Time (2)(3)
Fall Time (2)(3)
td(on)
tr
td(off)
tf
7
ns
15
ns
VDD ≈-25V, ID=-375mA
12 ns
15 ns
(1) Measured under pulsed conditions. Width=300µs. Duty cycle ≤2%
(2) Sample test.
(
3-421
3
)
Switching times measured with 50Ω source impedance and <5ns rise time on a pulse generator