ZVNL120A Datasheet, PDF (1/3 Pages) Zetex Semiconductors – N-CHANNEL ENHANCEMENT MODE VERTICAL DMOS FET

N-CHANNEL ENHANCEMENT
MODE VERTICAL DMOS FET
ISSUE 2 – MARCH 94
FEATURES
* 200 Volt V_DS
* R_DS(on)=10Ω
* Low threshold
ZVNL120A
APPLICATIONS
* Telephone handsets
ABSOLUTE MAXIMUM RATINGS.
PARAMETER
Drain-Source Voltage
Continuous Drain Current at T_amb=25°C
Pulsed Drain Current
Gate Source Voltage
Power Dissipation at T_amb=25°C
Operating and Storage Temperature Range
SYMBOL
V_DS
I_D
I_DM
V_GS
P_tot
T_j:T_stg
D
G
S
E-Line
TO92 Compatible
VALUE
200
180
2
± 20
700
-55 to +150
UNIT
V
mA
A
V
mW
°C
ELECTRICAL CHARACTERISTICS (at T_amb = 25°C unless otherwise stated).
PARAMETER
SYMBOL MIN. MAX. UNIT CONDITIONS.
Drain-Source Breakdown
Voltage
BV_DSS 200
V
I_D=1mA, V_GS=0V
Gate-Source Threshold
Voltage
V_GS(th) 0.5 1.5 V
ID=1mA, V_DS= V_GS
Gate-Body Leakage
I_GSS
100 nA V_GS=± 20V, V_DS=0V
Zero Gate Voltage Drain
I_DSS
Current
10 µA
100 µA
V_DS=200 V, V_GS=0
V_DS=160 V, V_GS=0V, T=125°C(2)
On-State Drain Current(1)
I_D(on)
500
mA V_DS=25 V, V_GS=5V
Static Drain-Source On-State R_DS(on)
Resistance (1)
10 Ω
10 Ω
V_GS=5V,I_D=250mA
V_GS=3V, I_D=125mA
Forward Transconductance g_fs
200
(1)(2)
mS V_DS=25V,I_D=250mA
Input Capacitance (2)
Common Source Output
Capacitance (2)
C_iss
C_oss
85 pF
20 pF V_DS=25 V, V_GS=0V, f=1MHz
Reverse Transfer Capacitance C_rss
(2)
7
pF
Turn-On Delay Time (2)(3)
Rise Time (2)(3)
Turn-Off Delay Time (2)(3)
Fall Time (2)(3)
t_d(on)
t_r
t_d(off)
t_f
8
ns
8
ns
V_DD ≈25V, I_D=250mA
20 ns
12 ns
(1) Measured under pulsed conditions. Width=300µs. Duty cycle ≤2% (2) Sample test.
(3) Switching times measured with 50Ω source impedance and <5ns rise time on a pulse generator
3-401