ZVN4206A Datasheet, PDF (1/3 Pages) Zetex Semiconductors – N-CHANNEL ENHANCEMENT MODE VERTICAL DMOS FET

N-CHANNEL ENHANCEMENT
MODE VERTICAL DMOS FET
ISSUE 2 – JUNE 94
FEATURES
* 60 Volt V_DS
* R_DS(on) = 1 Ω
ZVN4206A
D
G
S
ABSOLUTE MAXIMUM RATINGS.
PARAMETER
Drain-Source Voltage
Continuous Drain Current at T_amb=25°C
Pulsed Drain Current
Gate-Source Voltage
Power Dissipation at T_amb=25°C
Operating and Storage Temperature Range
SYMBOL
V_DS
I_D
I_DM
V_GS
P_tot
T_j:T_stg
E-LINE
TO92 COMPATIBLE
VALUE
60
600
8
± 20
0.7
-55 to +150
UNIT
V
mA
A
V
W
°C
ELECTRICAL CHARACTERISTICS (at T_amb = 25°C unless otherwise stated).
PARAMETER
SYMBOL MIN. MAX. UNIT CONDITIONS.
Drain-Source Breakdown
Voltage
BV_DSS
60
V
I_D=1mA, V_GS=0V
Gate-Source Threshold
Voltage
V_GS(th)
1.3
3
V
ID=1mA, V_DS= V_GS
Gate-Body Leakage
I_GSS
100 nA V_GS=± 20V, V_DS=0V
Zero Gate Voltage Drain
I_DSS
Current
10
µA V_DS=60V, V_GS=0
100 µA V_DS=48V, V_GS=0V, T=125°C(2)
On-State Drain Current(1)
I_D(on)
3
A
V_DS=25V, V_GS=10V
Static Drain-Source On-State R_DS(on)
Resistance (1)
1
Ω
1.5 Ω
V_GS=10V,I_D=1.5A
V_GS=5V,I_D=500mA
Forward Transconductance(1)(2g_fs
300
)
mS V_DS=25V,I_D=1.5A
Input Capacitance (2)
C_iss
Common Source Output
C_oss
Capacitance (2)
100 pF
60
pF V_DS=25V, V_GS=0V, f=1MHz
Reverse Transfer Capacitance C_rss
(2)
20
pF
Turn-On Delay Time (2)(3)
t_d(on)
8
ns
Rise Time (2)(3)
Turn-Off Delay Time (2)(3)
t_r
t_d(off)
12
ns
V_DD ≈25V, I_D=1.5A
12
ns
Fall Time (2)(3)
t_f
15
ns
(1) Measured under pulsed conditions. Width=300µs. Duty cycle ≤2% (2) Sample test.
(3) Switching times measured with 50Ω source impedance and <5ns rise time on a pulse generator