BSS123A Datasheet, PDF (1/1 Pages) Zetex Semiconductors – N-CHANNEL ENHANCEMENT MODE VERTICAL DMOS FET

SOT23 N-CHANNEL ENHANCEMENT
MODE VERTICAL DMOS FET
ISSUE 4 – APRIL 1998
FEATURES
* BV_DSS = 100V
* Low Threshold
PARTMARKING DETAIL
– SAA
BSS123A
S
D
G
ABSOLUTE MAXIMUM RATINGS.
PARAMETER
SYMBOL
VALUE
UNIT
Drain-Source Voltage
V_DS
100
V
Drain-Gate Voltage
V_DGR
100
V
Continuous Drain Current at T_amb=25°C
I_D
170
mA
Pulsed Drain Current
I_DM
680
mA
Gate-Source Voltage
V_GS
± 20
V
Power Dissipation at T_amb=25°C
P_tot
360
mW
Operating and Storage Temperature Range T_j:T_stg
-55 to +150
°C
ELECTRICAL CHARACTERISTICS (at T_amb = 25°C unless otherwise stated).
PARAMETER
SYMBOL MIN. TYP. MAX. UNIT CONDITIONS.
Drain-Source
Breakdown Voltage
BV_DSS 100
V
I_D=0.25mA, V_GS=0V
Gate-Source Threshold V_GS(th) 0.5
Voltage
2.0 V
I_D=1mA, V_DS= V_GS
Gate-Body Leakage
Zero Gate Voltage
Drain Current
I_GSS
I_DSS
50 nA
500 nA
V_GS=± 20V, V_DS=0V
V_DS=100V, V_GS=0V
Static Drain-Source
R_DS(on)
On-State Resistance (1)
Forward
g_fs
80
Transconductance(1)(2)
6
Ω
10 Ω
V_GS=10V, I_D=170mA
V_GS=4.5V, I_D=170mA
mS V_DS=25V, I_D=100mA
Input Capacitance (2)
Common Source
Output Capacitance (2)
C_iss
C_oss
25
pF
9
pF
V_DS=25V, V_GS=0V, f=1MHz
Reverse Transfer
C_rss
Capacitance (2)
4
pF
Turn-On Delay Time (2)(3) t_d(on)
10
ns
Rise Time (2)(3)
t_r
Turn-Off Delay Time (2)(3) t_d(off)
10
ns _{VDD ≈30V, ID=280mA}
15
ns
Fall Time (2)(3)
t_f
25
ns
(1) Measured under pulsed conditions. Width=300µs. Duty cycle ≤2% (2) Sample test.
(3) Switching times measured with 50Ω source impedance and <5ns rise time on a pulse generator