BS170P Datasheet, PDF (1/1 Pages) Zetex Semiconductors – N-CHANNEL ENHANCEMENT MODE VERTICAL DMOS FET

N-CHANNEL ENHANCEMENT
MODE VERTICAL DMOS FET
ISSUE 2 – SEPT 93
FEATURES
* 60 Volt V_DS
* R_DS(on)=5Ω
BS170P
REFER TO ZVN3306A FOR GRAPHS
ABSOLUTE MAXIMUM RATINGS.
PARAMETER
Drain-Source Voltage
Continuous Drain Current at T_amb =25°C
Pulsed Drain Current
Gate-Source Voltage
Power Dissipation at T_amb =25°C
Operating and Storage Temperature Range
SYMBOL
V_DS
I_D
I_DM
V_GS
P_tot
T_j:T_stg
D
G
S
E-Line
TO92 Compatible
VALUE
60
270
3
±20
625
-55 to +150
UNIT
V
mA
A
V
mW
°C
ELECTRICAL CHARACTERISTICS (at T_amb = 25°C).
PARAMETER
SYMBOL MIN. TYP. MAX. UNIT CONDITIONS.
Drain-Source
BV_DSS
60
Breakdown Voltage
V
I_D=100µA, V_GS=0V
Gate-Source
Threshold Voltage
V_GS(th)
0.8
3
V
I_D=1mA, V_DS=V_GS
Gate Body Leakage
Zero Gate Voltage
Drain Current
I_GSS
I_DSS
10
nA
VGS=15V, V_DS=0V
0.5
µA
V_GS=0V, V_DS=25V
Static Drain-Source
R_DS(on)
on-State Resistance (1)
5
Ω
V_GS=10V, I_D=200mA
Forward
g_fs
Transconductance (1)(2)
200
mS
V_DS=10V, I_D=200mA
Input Capacitance (2) C_iss
60
pF
V_GS=0V, V_DS=10V
f=1MHz
Turn-On Time (2)(3)
t_(on)
10
ns
V_DD≈15V, I_D=600mA
Turn-Off Time (2)(3)
t_(off)
10
ns
(1) Measured under pulsed conditions. Pulse width=300µs. Duty cycle ≤ 2% (2) Sample test
(3) Switching times measured with a 50Ω source impedance and <5ns rise time on a pulse generator
3-27