PSN1720A Datasheet, PDF (1/2 Pages) Z-Communications, Inc – LOW COST - HIGH PERFORMANCE PHASE LOCKED LOOP

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PSN1720A
PHASE LOCKED LOOP
Rev A1
PHASE NOISE (1 Hz BW, typical)
0
-40
-80
FEATURES
• Frequency Range: 1690 ^- 1760 _MHz
• Step Size:
50 _KHz
• _PLL - Style Package
APPLICATIONS
• Telecommunications
• Satellite
• Telemetry
-120
-160
-200
100 Hz
1 kHz
10 kHz
100 kHz
PERFORMANCE SPECIFICATIONS
Frequency Range
Phase Noise @ 10 kHz offset (1 Hz BW, typ.)
Harmonic Suppression (2nd, typ.)
Sideband Spurs (typ.)
Power Output
VALUE
1690 - 1760
-104
-15
-70
3.5±2.5
UNITS
MHz
dBc/Hz
dBc
dBc
dBm
Load Impedance
Step Size
Charge Pump Output Current
Switching Speed (typ., adjacent channel)
Startup Lock Time (typ.)
Operating Temperature Range
50
50
1000
4
6
-40 to 85
Ω
KHz
µΑ
mSec
mSec
°C
Package Style
PLL
POWER SUPPLY REQUIREMENTS
Supply Voltage (Vcc, nom.)
5
Supply Current (Icc, typ.)
33
All specifications are typical unless otherwise noted and subject to change without notice.
Vdc
mA
APPLICATION NOTES
• AN-107 : How to Solder Z-COMM VCOs / PLLs
• AN-200 : Mounting and Grounding of Z-COMM PLLs
• AN-201 : PLL Fundamentals
AN-202 : PLL Functional Description
NOTES:
Reference Oscillator Signal: 5 MHz<f _osc<40 MHz
Frequency Synthesizer: National Semiconductor - LMX2326
© Z-Communications, Inc.
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