MT312 Datasheet, PDF (77/90 Pages) Zarlink Semiconductor Inc – Satellite Channel Decoder

11.6 Primary 2-Wire Bus Timing
Microprocessor Control MT312
tBUFF
DATA1
tLOW
tR
Sr
P
tF
CLK1
P
t ^S
HD;STA
t t HD;DAT
HIGH
t t SU;DAT SU;STA
tSU;STO
Figure 26 - One DiSEqC™ data byte - 0x11 (hex) plus parity bit
Where: S = Start
Sr = Restart, i.e. Start without stopping first.
P = Stop.
Parameter: Primary 2-wire bus only
Symbol
CLK1 clock frequency
fCLK
Bus free time between a STOP and START condition.
tBUFF
Hold time (repeated) START condition.
tHD;STA
LOW period of CLK1 clock.
tLOW
HIGH period of CLK1 clock.
tHIGH
Set-up time for a repeated START condition.
tSU;STA
Data hold time (when input).
tHD;DAT
Data set-up time
tSU;DAT
Rise time of both CLK1 and DATA1 signals.
tR
Rise time of both CLK1 and DATA1 signals, (100pF to ground)
tF
Set-up time for a STOP condition.
tSU;STO
Table 8 - Primary 2-wire bus timing
Value
Unit
Min Max
0
450 kHz
200
ns
200
ns
450
ns
600
ns
200
ns
100
ns
100
ns
note 1 ns
20
ns
200
ns
Note 1.The rise time depends on the external bus pull up resistor.
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