ZL50021 Datasheet, PDF (73/136 Pages) Zarlink Semiconductor Inc – Enhanced 4 K Digital Switch with Stratum 3 DPLL

ZL50021
Data Sheet
External Read/Write Address: 0047_H
Reset Value: 000F_H
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1
0
LDT LDT LDT LDT LDT LDT LDT LDT LDT LDT LDT LDT LDT LDT LDT LDT
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Bit
Name
Description
15 - 0
LDT15 - 0
Lock Detect Threshold Bits: The binary value of these bits defines the upper limit of the
absolute phase from the phase detector output for lock detection.
When the value of the absolute phase is less than or equal to LDT for duration of time
defined by the LDIR register, the DPLL locks.
When the value of the absolute phase is greater than LDT for duration of time defined by
the LDIR register divided by 256, the DPLL does not lock.
Note: LDT should be calculated as per the maximum expected amplitude of jitter on the active input reference
using the following formula:
LDT = MAX_EXP_JITTER (ns) x 2
15.2 (ns)
Example: If maximum expected jitter amplitude on 2.048 MHz reference is 10UI (i.e., 10 x 488.2 ns = 4882 ns)
(assuming the jitter frequency where DPLL attenuation is big), the LDT should be programmed to be (4882/15.2)
x 2 = 642 = 0282_H
Table 36 - Lock Detector Threshold Register (LDTR) Bits
External Read/Write Address: 0048_H
Reset Value: 2C00_H
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0
LDI
LDI
LDI
LDI
LDI
LDI
LDI
LDI
LDI
LDI
LDI
LDI
LDI
LDI
LDI
LDI
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0
Bit
15 - 0
Name
Description
LDI15 - 0
Lock Detector Interval Bits: The binary value of these bits defines the time interval that
the output phase detector must be below the lock detect threshold to declare lock.
Unsigned representation of the LDI bits is defined in 4ms intervals.
Table 37 - Lock Detector Interval Register (LDIR) Bits
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Zarlink Semiconductor Inc.