PDSP1601_98 Datasheet, PDF (7/16 Pages) Zarlink Semiconductor Inc – ALU and Barrel Shifter

PDSP1601/PDSP1601A
SV3 SV2 SV1 SV0
Shift
00
00
00
00
01
01
01
01
10
10
10
10
11
11
11
11
0
0
No shift
0
1
1 place
1 0 2 places
1 1 3 places
0 0 4 places
0 1 5 places
1 0 6 places
1 1 7 places
0 0 8 places
0 1 9 places
1 0 10 places
1 1 11 places
0 0 12 places
0 1 13 places
1 0 14 places
1 1 15 places
Table 3 Barrel shifter codes
Priority Encoder
If the priority encoder is selected as the source of the shift
value (instructions:- NRMXX, NRMR1, MRMRZ), then within
one 100ns cycle or two 50ns cycles for the PDSP1601A (one
200ns or two 100ns cycles for the PDSP1601), the shift
circuitry will:
(1) Priority encode the 16 bit input to the Barrel Shifter and
place the 4 bit value in either of the R1 or R2 registers and
output the value on the SV port (if enabled by SVOE).
(2) Shift the 16 bit input by the amount indicated by the
Priority Encoder such that the output from the Barrel Shifter is
a normalised value.
SV Input
If the SV port is selected as the source of the shift value,
then the input to the Barrel Shifter is shifted by the value stored
in the internal SV register.
SVOE
The SV port acts as an input or an output depending upon
the IS0-3 instruction. If the user does not wish to use the
normalise instructions, then the SV port mat be forced to be
input only by typing SVOE control high. In this mode the SV
port may be considered an extension of the instruction inputs.
R1 and R2 Registers
The R1 and R2 registers may be loaded from the Priority
Encoder (NRMR1 and NRMR2) or from the SV input (LR1SV,
LR2SV).
Whilst the latter two instructions are executing, the Barrel
Shifter will pass its input to the output unshifted.
16
PRIORITY ENCODER
INSTRUCTION
DECODE
4
IS0-3
4
MUX
MUX
R1
MUX
R2
4
SV
SVOE
Fig.3 Shift control block
7