ZL30119 Datasheet, PDF (6/27 Pages) Zarlink Semiconductor Inc – Low Jitter Line Card Synchronizer

ZL30119
Data Sheet
Pin Description
Pin #
Name
I/O
Type
Description
Input Reference
C1
ref0
B2
ref1
A3
ref2
C3
ref3
B3
ref4
B4
ref5
C4
ref6
A4
ref7
I_d Input References (LVCMOS, Schmitt Trigger). These are input references
available to both DPLL1 and DPLL2 for synchronizing output clocks. All eight
input references can be automatically or manually selected using software
registers. These pins are internally pulled down to Vss.
B1
sync0
A1
sync1
A2
sync2
I_d Frame Pulse Synchronization References (LVCMOS, Schmitt Trigger).
These are the frame pulse synchronization inputs associated with input
references 0, 1 and 2. These inputs accept frame pulses in a clock format (50%
duty cycle) or a basic frame pulse format with minimum pulse width of 5 ns.
These pins are internally pulled down to V_ss.
Output Clocks and Frame Pulses
D10
sdh_clk0
O SONET/SDH Output Clock 0 (LVCMOS). This output can be configured to
provide any one of the SONET/SDH clock outputs up to 77.76 MHz. The default
frequency for this output is 77.76 MHz.
G10
sdh_clk1
O SONET/SDH Output Clock 1 (LVCMOS). This output can be configured to
provide any one of the SONET/SDH clock outputs up to 77.76 MHz. The default
frequency for this output is 19.44 MHz.
E10
sdh_fp0
O SONET/SDH Output Frame Pulse 0 (LVCMOS). This output can be configured
to provide virtually any style of output frame pulse synchronized with an
associated SONET/SDH family output clock. The default frequency for this frame
pulse output is 8 kHz.
F10
sdh_fp1
O SONET/SDH Output Frame Pulse 1 (LVCMOS). This output can be configured
to provide virtually any style of output frame pulse synchronized with an
associated SONET/SDH family output clock. The default frequency for this frame
pulse output is 2 kHz.
K9
p0_clk0
O Programmable Synthesizer 0 - Output Clock 0 (LVCMOS). This output can be
configured to provide any frequency with a multiple of 8 kHz up to 77.76 MHz in
addition to 2 kHz. The default frequency for this output is 2.048 MHz.
K7
p0_clk1
O Programmable Synthesizer 0 - Output Clock 1 (LVCMOS). This is a
programmable clock output configurable as a multiple or division of the p0_clk0
frequency within the range of 2 kHz to 77.76 MHz. The default frequency for this
output is 8.192 MHz.
K8
p0_fp0
O Programmable Synthesizer 0 - Output Frame Pulse 0 (LVCMOS). This output
can be configured to provide virtually any style of output frame pulse associated
with the p0 clocks. The default frequency for this frame pulse output is 8 kHz.
J7
p0_fp1
O Programmable Synthesizer 0 - Output Frame Pulse 1 (LVCMOS). This output
can be configured to provide virtually any style of output frame pulse associated
with the p0 clocks. The default frequency for this frame pulse output is 8 kHz.
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Zarlink Semiconductor Inc.