VP5311C Datasheet, PDF (6/19 Pages) Zarlink Semiconductor Inc – NTSC/PAL Digital Video Encoder

VP5311C/VP5511C
PIN DESCRIPTIONS
Pin Name
Pin No. Description
PD7-0
D0-7
PXCK
CLAMP
COMPSYNC
30 - 37
1-8
12
14
15
8 Bit Pixel Data inputs clocked by PXCK. PD0 is the least significant bit, corresponding to Pin
37. These pins are internally pulled low.
8 Bit General Purpose Port input/output. D0 is the least significant bit, corresponding to Pin 1.
These pins are internally pulled low.
27MHz Pixel Clock input. The VP5311C/5511C internally divides PXCK by two to provide the
pixel clock.
The CLAMP output signal is synchronised to COMPSYNC output and indicates the position of
the BURST pulse, (lines 10-263 and 273-525 for NTSC and PAL-M; lines 6-310 and 319-623
for PAL-B,D, G,I,N(Argentina)).
Composite sync pulse output. This is an active low output signal.
TDO
TDI
TMS
TCK
SA1
SA2
SCL
SDA
RESET
REFSQ
VREF
DAC GAIN
COMP
LUMAOUT
COMPOUT
CHROMAOUT
VDD
AVDD
GND
AGND
16
17
18
19
21
22
23
25
27
28
41
42
43
45
47
49
10, 13, 24,
26, 39
44, 50,
51, 52
9, 11, 20,
29, 38
40, 46, 48
JTAG Data output port.
JTAG Data input port.
JTAG mode select input.
JTAG clock input.
I²C slave address select
I²C slave address select.
Standard I²C bus serial clock input.
Standard I²C bus serial data input/output.
Master reset. This is an asynchronous, active low, input signal and must be asserted for a
minimum 200ns in order to reset the VP5311C/5511C.
Reference square wave input used only during Genlock mode.
Voltage reference input/output. This pin is nominally 1.055V and should be decoupled with a
100nF capacitor to GND.
DAC full scale current control. A resistor connected between this pin and GND sets the
magnitude of the video output current. An internal loop amplifier controls a reference current
flowing through this resistor so that the voltage across it is equal to the Vref voltage.
DAC compensation. A 100nF ceramic capacitor must be connected between pin 43 and pin
44.
True luminance, composite and chrominance video signal outputs. These are high
impedance current source outputs. A DC path to GND must exist from each of these pins.
Positive supply input. All VDD pins must be connected.
Analog positive supply input. All AVDD pins must be connected.
Negative supply input. All GND pins must be connected.
Negative supply input. All AGND pins must be connected.
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