MV95308 Datasheet, PDF (6/9 Pages) Zarlink Semiconductor Inc – 30MHz 8-BIT CMOS VIDEO DAC

MV95308
Pin
2
3-10
13,15
14
20
11
12
1
17
19
18
16
Name Description
CLK
The clock input. The falling edge of the clock latches the DATA, BLANK, SYNC, OVERBRT and
REFWHITE inputs into the logic pipeline. The decoded data will be latched into the DAC output 1
clock cycle later. The clock frequency determines the update rate of the DAC output.
D₇-D₀
I_OUT, I_OUT
The data inputs. D₀ is the least significant bit (LSB). The coding is in straight binary only.
The current output and its complement. These are the high impedance current source outputs of
the DAC capable of driving a 75Ω load up to a voltage of 1.5V.
GND
Analog ground for the DAC.
V_DD
V_REF
Analog power for the DAC
The output of the internal voltage reference generator. This output is nominally 1V, and
should be decoupled with a 10nF capacitor.
R_SET
The full scale adjust control. The R_SET resistor is connected from this pin to ground. An internal
loop amplifier adjusts a reference current flowing through the R_SET resistor so that the voltage
across the resistor is equal to the V_REF voltage. This reference current has a weighting equal to
16 LSB’s.
BLANK
The composite blank control input. A logical zero on this input removes the Black pedestal
from the I_OUT output, whilst forcing the internal data to the DAC to $00. This input is latched on
the clock falling edge and will override the REFWHITE and OVERBRT inputs. The Black
pedestal is 7.5 IRE units (actually 21 LSB’s). If left open circuit this input is internally tied high.
SYNC
The composite sync control input. A logical zero on this input removes the Blank pedestal
from the I_OUT output. The Blank pedestal is nominally 40 IRE units (actually 111 LSB’s). The
SYNC input does not override any other control lines. This input is latched on the clock falling
edge. If left open circuit this input is internally tied high.
REFWHITE The reference white level control input. A logical zero on this input overrides the input data,
forcing the data to $FF. The BLANK input will override this input. If left open circuit this input is
internally tied high.
OVERBRT
The 10% overbright control input. A logical zero on this input switches the Overbright pedestal
into the I_OUT output. The Overbright pedestal is 10 IRE units (actually 27 LSB’s). This input does
not override any other input. The BLANK input overrides this input. If left open circuit this input is
internally tied high.
STRDAC
The straight DAC control input. A logical zero on this input causes the Black, Blank and
Overbright pedestals to be disabled, removing them from both I_OUT and I_OUT. This allows the
DAC contribution to the output to be extended to a full 1 Volt. To obtain this extra DAC range, it is
necessary to reduce the R_SET resistor value, see application notes. The BLANK the REFWHITE
inputs may still be used to force the input data to $00 or $FF respectively. With the STRDAC pin
held low the output current can be calculated from:
Output current = Data x 1 LSB
Where 1 LSB=
V_REF
16 x R_SET
Full scale = 255 LSB
V_REF = 1.0V typ.
The exact value of 1 LSB must be calculated from the full scale output.
If left open circuit this input is internally tied high and the device will be configured for video graphics.
In this mode the output current can be calculated from:
Output current = (DATA + 21 + 111) x 1 LSB
V_REF = 1.0V typ.
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