KESRX05 Datasheet, PDF (6/28 Pages) Zarlink Semiconductor Inc – 260 to 470MHz ASK Receiver with Power Down

KESRX05
Pin Name
15 DSN
16 LF
17 V_EE
18 VCO2
19 VCO1
20 DF2
21 DF1
Function
Schematic
Data slice reference level
The DSN pin is defined internally by the Slice volt-
age V_REF. The DSN slice voltage can be offset from
the internal reference V_REF by connecting a resistor
from the DSN pin to V_EE and/or the peak detector
output.
For further information please refer to the Baseband
section of the Functional Description.
3k
DSN
100k
VREF
(VBE)
VEE
DF2
3k
HYSTERESIS
25mV
PLL loop filter connection
The phase detector output current is derived by two
internal current sources. The nominal linear average
output current is 115µA (5µA/radian).
For further information please refer to the Phase Lock
Loop VCO section of the Functional Description
UP
DOWN
115µA
LF
215µA
Negative supply
Voltage controlled oscillator
The voltage controlled oscillator circuit is designed
from two cross coupled transistors. The centre fre-
quency of the VCO is set by the external tank circuit.
For further information please refer to the Voltage
Controlled Oscillator (VCO) Circuit Design / Layout
section of the Functional Description
1·4k
50
VCO1
V_CC
1·4k
50
VCO2
300µA
Voltage controlled oscillator
See pin 18
Data Filter Output
The data filter is configured as a unity gain amplifier
with a low impedance output. Tracking of the received
baseband signal is achieved by an internal current
source.
For further information please refer to the Baseband
section of the Functional description.
3k
DSN
100k
VREF
(VBE)
VEE
DF2
3k
HYSTERESIS
25mV
Data filter input
Input to data filter. Bandwidth of second order Sallen
and Key data filter is set by external components
R10, R1 1, C5 and C6.
DF1
For further information please refer to the Baseband
section of the Functional Description.
Table 1 Pin descriptions (continued)
Cont…
5