ZL30416 Datasheet, PDF (5/22 Pages) Zarlink Semiconductor Inc – SONET/SDH Clock Multiplier PLL

ZL30416
Data Sheet
2.2 Frequency/Phase Detector
The Frequency/Phase Detector compares the frequency/phase of the input reference signal with the feedback
signal from the Frequency Divider circuit and provides an error signal equal to the frequency/phase
difference between the two. This error signal is passed to the Loop Filter circuit.
2.3 Lock Indicator
The ZL30416 has a built-in LOCK detector that measures frequency difference between input reference clock C19i
and the VCO frequency. When the VCO frequency is less than ±300 ppm apart from the input reference frequency
then the LOCK output is set high. The LOCK output is pulled low if the frequency difference exceeds ±1000 ppm.
2.4 Loop Filter
The Loop Filter is a low-pass filter. This low-pass filter eliminates high frequency spectral components from a phase
error signal produced by the Phase Detector. This ensures low output jitter that meets network jitter requirements.
The corner frequency of the Loop Filter is configurable with an external capacitor and resistor connected to the LPF
ball and ground as shown in Figure 3.
Frequency
and Phase
Detector
VCO
ZL30416
Loop
Filter
LPF
R_F
C_F
R_F=8.2 kΩ, C_F=470 nF
f_TYP=14.4 kHz
Figure 3 - Loop Filter Elements
2.5 VCO
The voltage-controlled oscillator (VCO) receives the filtered error signal from the Loop Filter and based on the
voltage of the error signal generates a primary frequency. The VCO output is connected to the "Frequency Dividers
and Clock Drivers" block that divides VCO frequency and buffer generated clocks.
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