ZL30407 Datasheet, PDF (47/57 Pages) Zarlink Semiconductor Inc – SONET/SDH Network Element PLL

ZL30407
AC Electrical Characteristics - Input to Output Phase Offset (after phase realignment)*
Characteristics
Symbol Min. Max. Units
1 8 kHz ref: pulse width high or low
t_R8W
100
ns
2 8 kHz ref input to F8o delay
t_R8D
-6
29
ns
3 1.544 MHz ref: pulse width high or low
t_R1.5W
100
ns
4 1.544 MHz ref input to F8o delay
t_R1.5D
335
350
ns
5 2.048 MHz ref: pulse width high or low
t_R2W
100
ns
6 2.048 MHz ref input to F8o delay
t_R2D
255
272
ns
7 19.44 MHz ref: pulse width high or low
t_R19W
20
ns
8 19.44 MHz ref input to F8o delay
t_R19D
8
21
ns
9 F8o to C19o delay
t_C19D
-5
7
ns
10 Reference input rise and fall time
t_IR, t_IF
10
ns
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
Data Sheet
Notes
t_R8W
t_R8D
PRI/SEC
8 kHz
V_T
tc = 125 µs
t_R1.5W
t_R1.5D
PRI/SEC
V_T
1.544 MHz
tc = 647.67 ns
t_R2W
t_R2D
PRI/SEC
2.048 MHz
tc = 488.28 ns
PRI/SEC
19.44 MHz
C19o
tc = 51.44 ns
tc = 51.44 ns
F8o
tc = 125 µs
t_R19W
V_T
t_R19D
V_T
t_C19D
V_T
V_T
Note: Delay time measurements are done with jitter free input reference signals.
Figure 21 - Input Reference to Output Clock Phase Offset
47
Zarlink Semiconductor Inc.