ZL50073_06 Datasheet, PDF (45/68 Pages) Zarlink Semiconductor Inc – 32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Streams (8, 16, 32 or 64 Mbps), and 128 Inputs and 128 Outputs

ZL50073
Data Sheet
External Read/Write Address: 40200_H - 4027F_H
Reset Value: 000C000C_H
31 30 29 28 27 26 25
0
0
0
0
0
0
0
15 14 13 12 11 10 9
0
0
0
0
0
0
ISI
24
0
8
ISPD
4
23
0
7
ISPD
3
22
OSI
6
ISPD
2
21 20
19
18
17
16
OSBA 1 OSBA 0 OSBR 1 OSBR 0 OSSRC 1 OSSRC 0
5
ISPD
1
4
ISPD
0
3
ISBR
1
2
ISBR
0
1
ISSRC
1
0
ISSRC
0
Bit
Name
Description
19 - 18
OSBR1 - 0 Output Stream Bit Rate
OSBR1 - 0
00
01
10
11
STi/oA
8.192 Mbps
16.384 Mbps
32.768 Mbps
65.536 Mbps
Bit Rates Per Group
STi/oB
8.192 Mbps
16.384 Mbps
32.768 Mbps
Not Used
STi/oC
8.192 Mbps
16.384 Mbps
Not Used
Not Used
STi/oD
8.192 Mbps
16.384 Mbps
Not Used
Not Used
17 - 16
OSSRC1 - 0
Unused streams are tri-stated.
If the internal system clock is used as the clock source, all the above data rates are
available. Otherwise, the data rate cannot exceed the selected clock source’s rate.
Output Stream Clock Source Select
OSSRC1 - 0
00
01
10
11
Output Timing Source
Internal System Clock
CKi0 and FPi0
CKi1 and FPi1
CKi2 and FPi2
15 - 10
9
8-4
Unused
ISI
ISPD4 - 0
Reserved. In normal functional mode, these bits MUST be set to zero.
Input Stream Inversion
For normal operation, this bit is set low.
To invert the input stream, set this bit high.
Input Sampling Point Delay
Default Sampling Point is 3/4. Adjust according to Figure 5 on page 20.
Table 25 - Group Control Register (continued)
45
Zarlink Semiconductor Inc.