ZL30410 Datasheet, PDF (4/38 Pages) Zarlink Semiconductor Inc – Multi-service Line Card PLL

Pin Description
Pin #
1
2-5
6
7, 8
9
Name
IC
NC
GND
NC
FCS
10
VDD
11
GND
12
F16o
13
C16o
14
C8o
15
C4o
16
C2o
17
F0o
18
MS1
19
MS2
20
F8o
ZL30410
Data Sheet
.
Description
Internal Connection. Leave unconnected.
No internal bonding Connection. Leave unconnected.
Ground. Negative power supply.
No internal bonding Connection. Leave unconnected.
Filter Characteristic Select (Input). In Hardware Control, FCS selects the
filtering characteristics of the ZL30410. Set this pin high to have a loop filter
corner frequency of 6 Hz and limit the phase slope to 41 ns per 1.326 ms. Set
this pin low to have corner frequency of 12 Hz with no phase slope limiting
imposed. This pin is internally pulled down to GND.
Positive Power Supply.
Ground.
Frame Pulse ST-BUS 8.192 Mb/s (CMOS tristate output). This is an 8 kHz,
61ns wide, active low framing pulse, which marks beginning of a ST-BUS
frame. This frame pulse is typically used for ST-BUS operation at 8.192 Mb/s.
Clock 16.384 MHz (CMOS tristate output). This clock is used for ST-BUS
operation at 8.192 Mb/s.
Clock 8.192 MHz (CMOS tristate output). This clock is used for ST-BUS
operation at 8.192 Mb/s.
Clock 4.096 MHz (CMOS tristate output). This clock is used for ST-BUS
operation at 2.048 Mb/s.
Clock 2.048 MHz (CMOS tristate output). This clock is used for ST-BUS
operation at 2.048 Mb/s.
Frame Pulse ST-BUS 2.048 Mb/s (CMOS tristate output). This is an 8 kHz,
244ns, active low framing pulse, which marks the beginning of a ST-BUS
frame. This is typically used for ST-BUS operation at 2.048 Mb/s and 4.096
Mb/s.
Mode Select 1 (Input). The MS1 and MS2 pins select the ZL30410 mode of
operation (Normal, Holdover or Free-run), see Table 1 on page 14 for details.
The logic level at this input is sampled by the rising edge of the F8o frame
pulse.
Mode Select 2 (Input). The MS2 and MS1 pins select the ZL30410 mode of
operation (Normal, Holdover or Free-run), see Table 1 on page 14 for details.
The logic level at this input is sampled by the rising edge of the F8o frame
pulse.
Frame Pulse ST-BUS/GCI 8.192 Mb/s (CMOS tristate output). This is an 8
kHz, 122 ns, active high framing pulse, which marks the beginning of a
ST-BUS/GCI frame. This is typically used for ST-BUS/GCI operation at 8.192
Mb/s. See Figure 15 for details.
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Zarlink Semiconductor Inc.