ZIF600 Datasheet, PDF (4/9 Pages) Zarlink Semiconductor Inc – Pager Synthesiser and 4FSK Demodulator

ZIF600
DESCRIPTION OF FUNCTIONS
Pin No.
Pin Name
Pin Type
Description
1
RXQ
In
Receiver "Quadrature" output
2
RXI
In
Receiver "In Phase" output
3
SRF
In
Symbol Rate Filter
4
DATA0
Out
Data output to decoder
5
DATA1
Out
Data output to decoder
6
VSSD
G
Digital Ground
7
VDDD
P
2.7 to 3.3V Digital Power Supply
8
VREF
In
1.25 Volt Reference from ZIF100
9
RBIAS
In
Bias setting Resistor 120kΩ to VSSA max. parasitic capacitance = 5pF
10
PDOUT
Out
Charge pump output from synthesiser
11
PLLC
In
Synthesiser power down
12
DACOUT
Out
Trim DAC for crystal
13
VSS1
G
Ground (substrate)
14
REFOSC
I/O
Reference Oscillator
15
TSS
In
Test Scan Select, Normally logic 0
16
REFOSCB
I/O
Reference Oscillator. External resistor to VDD1
17
VDDA
P
2.7 to 3.3V Analog Power Supply
18
VCOFIN
In
VCO frequency input to synthesiser
19
VSSA
G
Analog Ground
20
CLOCK
In
Control Bus Clock
21
LE
In
Control Bus Latch Enable
22
DATA
In
Control Bus Data
23
DSC1
In
With DSC2 controls the operating mode of the demodulator
24
DSC2
In
With DSC1 controls the operating mode of the demodulator
Table 1. List of pins
FUNCTIONAL DESCRIPTION
The ZIF600 synthesiser is used to select the channel in
4FSK paging receivers and uses on-chip constant current
charge pumps to drive an external passive loop filter. Common
low cost reference crystals are used, at frequencies of 12.8 or
14.4MHz, and are divided to give the required 12.5, 20 or
25kHz channel spacings. The reference crystal oscillator uses
external trimming to meet system requirements and is controlled
by a DAC set by the digital demodulator.
The digital demodulator takes the limited I and Q signals
from the radio receiver and converts the 4-level FSK into 2 bit
data output on pins DATA0 and DATA1. An AFC output from
this demodulator is also included.
Functions are controlled by a serial bus with a simple
programming format and with four control pins to allow optimum
power up sequences which help minimise the system current
consumption.
Crystal Comp. Total RD1
MHz freq. kHz division
RD2
RD3
REFERENCE DIVIDERS
The reference frequency generated by the oscillator on
pins REFOSC and REFOSCB is divided to give the comparison
frequency clock. See Fig. 3.
Ratio selection is five control bits RD1 (where LOW gives
÷ 8 mode), RD2 (where LOW gives ÷ 4 mode) and RD3 (where
LOW gives ÷ 2 mode) which can be set to give the 8 options
needed to get 10kHz, 12.5kHz, 20kHz or 25kHz from either a
12.8 or 14.4MHz crystal, as in Table 2. The additional control
bits RD4 and RD5 allow the option of further division to allow
for an off chip frequency multiplier. If both RD4 and RD5 are set
low then this division stage is bypassed. Other settings for RD4
and RD5 offer division by 2, 3 or 4. Table 3 shows the additional
division options available from RD4 and RD5.
Power down options are available for both the synthesiser
and demodulator, however the crystal oscillator and the
reference divider must be kept running to give a timing signal
to the demodulator whilst the demodulator is on.
12.8
25
512
0
0
0
14.4
25
576
1
0
0
12.8
20
640
0
1
0
Additional division
RD4
RD5
14.4
20
720
1
1
0
12.8
12.5 1024
0
0
1
14.4
12.5 1152
1
0
1
12.8
10
1280
0
1
1
14.4
10
1440
1
1
1
Bypass
2
3
4
0
0
0
1
1
0
1
1
Table 2 Reference divider ratios
Table 3 Additional divider ratios
3