KESRX01 Datasheet, PDF (4/11 Pages) Zarlink Semiconductor Inc – 290 - 460MHz ASK Receiver

KESRX01
External SAW resonator
For reduced power the PLL based oscillator can be
replaced by a SAW based oscillator. If pin PD is tied low (VEE)
the crystal oscillator, dividers and phase detector/charge
pump are powered down. The VCO can then be used as a
maintaining amplifier for an external SAW based oscillator.
The normal mode of operation is with PD set high (VCC) or
alternatively left unconnected. Note: the power down facility
is intended to be hard wired (either to VCC or VEE) and hence
the PD pin is not specified for operation with normal CMOS or
TTL logic levels.
PD
V CC /NC
V EE
MODE
PLL Enable
PLL Disable
Reference crystal oscillator
A crystal stabilised oscillator provides a reference clock for
the PLL. The oscillator is configured for parallel resonant
operation in the fundamental mode (typical operating
frequency of 4–7MHz). The crystal is connected between pins
XTAL1, XTAL2 with external components as shown in Fig. 6.
Note that this is a single transistor Colpitts oscillator where the
external load capacitors must be taken into account in
specifying the crystal. See Application Note AN207.
RF amplifier
The RF amplifier consists of a low noise transistor in a
common emitter configuration. A separate emitter connection
is provided (VEERF) to reduce sensitivity to any common
impedance in this path. The amplifier is current source biased
so the signal (RFIN) should be a.c. coupled. The collector is
open circuit so that the gain can be set with an external tuned
load, Fig. 6. Its input impedance is given in Fig. 9 and output
impedance in Fig. 10.
Down converting mixer
The RF input is a.c. coupled into a doubly balanced mixer
configuration. Its input impedance is given in Fig.8.
IF filtering
The IF filter has a (nominal) bandpass response from
25KHz to 550KHz. The single high pass section is provided by
the combination of the external a.c. coupling capacitor
between IF1 and IF2 and an on chip resistor (nominal value
12kΩ). The low pass section is entirely on chip and to meet the
selectivity requirements (adjacent channel rejection) this filter
has 4 low pass poles with a Butterworth response.
IF amplifiers and demodulator
The majority of the receiver gain is provided in the form of
an IF limiting strip. These amplifiers are all d.c. coupled and
hence differential d.c. feedback is required. This is decoupled
externally at pins IFDC1 and IFDC2. The IF amplifier stages
also combine to provide a Received Signal Strength Indicator
(RSSI) function. Since the modulation is ASK and the RSSI
output has
a linear output for a logarithmic change on its input then the
RSSI output is the demodulated data. The only uncertainty is
the d.c. level.
Data filter
Prior to the data slicer the demodulated data passes through
a low pass filter. This filter is a 2nd order Sallen–Key section
using an on chip voltage follower. External capacitors set the
cutoff frequency and filter Q. The value of the on chipresistors
is 100KΩ (nominal). See Fig. 4.
The cut-off frequency of the data filter,ƒo, should be set to
reduce high frequency noise into the data slicer without
distorting the wanted signal. Normally this would be at least
three times the data frequency.
C1
R
R DF1
DF0 _100K
DF2
C2
BESSEL
Q = 0.577
Y = 1.732
BUTTERWORTH
Q = 0.71
Y = 1.0
CUT OFF FREQUENCY = fo
ω_o = 2 . π . fo . y
C1 = 2.Q
R . ω_o
C2 = 1
2 . Q . R ω_o.
Fig. 4 Choosing data filter components
Example
To implement a Bessel response filter with a 10KHz 3dB cutoff
C1 = 106pF
C2 = 80pF
4