ZL50016 Datasheet, PDF (38/81 Pages) Zarlink Semiconductor Inc – Enhanced 1 K Digital Switch

ZL50016
19.0 Detailed Register Description
Data Sheet
External Read/Write Address: 0000_H
Reset Value: 0000_H
15 14
13
12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
OPM
0
FPIN CKINP FPINP CKIN CKIN VAR MBPE OSB MS1 MS0
POS
1
0
EN
Bit
Name
Description
15 - 12 Unused Reserved. In normal functional mode, these bits MUST be set to zero.
11
OPM Operation Mode.
This bit is used to set the device in Master/Slave operation. Refer to Table 7, “ZL50016
Operating Modes” on page 31 for more details.
10
Unused Reserved. In normal functional mode, this bits MUST be set to zero.
9
FPINPOS Input Frame Pulse (FPi) Position
When this bit is low, FPi straddles frame boundary (as defined by ST-BUS).
When this bit is high, FPi starts from frame boundary (as defined by GCI-Bus)
8
CKINP Clock Input (CKi) Polarity
When this bit is low, the CKi falling edge aligns with the frame boundary.
When this bit is high, the CKi rising edge aligns with the frame boundary.
7
FPINP Frame Pulse Input (FPi) Polarity
When this bit is low, the input frame pulse FPi has the negative frame pulse format.
When this bit is high, the input frame pulse FPi has the positive frame pulse format.
6 - 5 CKIN1 - 0 Input Clock (CKi) and Frame Pulse (FPi) Selection
CKIN1 - 0
00
01
10
11
FPi Active Period
CKi
61 ns
122 ns
244 ns
16.384 MHz
8.192 MHz
4.096 MHz
Reserved
The MODE_4M0 and MODE_4M1 pins, as described in “Pin Description” on page 10,
should also be set to define the input clock mode.
4
VAREN Variable Delay Mode Enable
When this bit is low, the variable delay mode is disabled on a device-wide basis.
When this bit is high, the variable delay mode is enabled on a device-wide basis.
3
MBPE Memory Block Programming Enable
When this bit is high, the connection memory block programming mode is enabled to
program the connection memory. When it is low, the memory block programming mode is
disabled.
Table 13 - Control Register (CR) Bits
38
Zarlink Semiconductor Inc.