ZL38070 Datasheet, PDF (35/51 Pages) Zarlink Semiconductor Inc – 256 Channel Voice Echo Canceller

ZL38070
Data Sheet
Power-up
0C_hex
Bit 7
NLP15
ECA: Non-Linear Processor Threshold Register 2
(NLPTHR)
Page 0
ECB: Non-Linear Processor Threshold Register 2
(NLPTHR)
A12=0
A11=0
Bit 6
NLP14
Bit 5
NLP13
Bit 4
NLP12
Bit 3
NLP11
Bit 2
NLP10
R/W Address:
19_hex + Base Address
R/W Address:
39_hex + Base Address
Bit 1
Bit 0
NLP9
NLP8
Power-up
E0_hex
ECA: Non-Linear Processor Threshold Register 1
(NLPTHR)
ECB: Non-Linear Processor Threshold Register 1
(NLPTHR)
Page 0
A12=0
A11=0
R/W Address:
18_hex + Base Address
R/W Address:
38_hex + Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NLP7
NLP6
NLP5
NLP4
NLP3
NLP2
NLP1
NLP0
Functional Description of Register Bits
This register allows the user to program the level of the Non-Linear Processor Threshold (NLPTHR). The 16
bit 2’s complement linear value defaults to 0CE0_hex = 0.1 or -20.0 dB. The maximum value is 7FFF_hex =
0.9999 or 0 dB.
Power-up
40_hex
Bit 7
MU15
ECA: Adaptation Step Size Register 2 (MU)
ECB: Adaptation Step Size Register 2 (MU)
Bit 6
MU14
Bit 5
MU13
Bit 4
MU12
Bit 3
MU11
Page 0
A12=0
A11=0
Bit 2
MU10
R/W Address:
1B_hex + Base Address
R/W Address:
3B_hex + Base Address
Bit 1
Bit 0
MU9
MU8
Power-up
00_hex
ECA: Adaptation Step Size Register 1 (MU)
ECB: Adaptation Step Size Register 1 (MU)
Page 0
A12=0
A11=0
R/W Address:
1A_hex + Base Address
R/W Address:
3A_hex + Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MU7
MU6
MU5
MU4
MU3
MU2
MU1
MU0
Functional Description of Register Bits
This register allows the user to program the level of MU, which is the LMS filter step size. Increasing this
value can speed up convergence times, but can also potentially decrease VEC stability. MU is a 16 bit 2’s
complement value which defaults to 4000_hex = 1.0 The maximum value is 7FFF_hex or 1.9999 decimal. The
high byte is in Register 2 and the low byte is in Register 1.
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Zarlink Semiconductor Inc.