ZL50212 Datasheet, PDF (34/42 Pages) Zarlink Semiconductor Inc – 288 Channel Voice Echo Canceller

ZL50212
Data Sheet
Power-up
N/A
Bit 7
RP15
Bit 6
RP14
ECA: Rin Peak Detect Register 2 (RP)
ECB: Rin Peak Detect Register 2 (RP)
Bit 5
RP13
Bit 4
RP12
Bit 3
RP11
Bit 2
RP10
R/W Address:
0D_hex + Base Address
R/W Address:
2D_hex + Base Address
Bit 1
Bit 0
RP9
RP8
Power-up
ECA: Rin Peak Detect Register 1 (RP)
R/W Address:
N/A
0C_hex + Base Address
ECB: Rin Peak Detect Register 1 (RP)
R/W Address:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
2C_hex + Base Address
Bit 1
Bit 0
RP7
RP6
RP5
RP4
RP3
RP2
RP1
RP0
Functional Description of Register Bits
These peak detector registers allow the user to monitor the receive in (Rin) peak signal level. The information
is in 16-bit 2’s complement linear coded format presented in two 8 bit registers for each echo canceller. The
high byte is in Register 2 and the low byte is in Register 1.
Power-up
N/A
Bit 7
SP15
Bit 6
SP14
ECA: Sin Peak Detect Register 2 (SP)
ECB: Sin Peak Detect Register 2 (SP)
Bit 5
SP13
Bit 4
SP12
Bit 3
SP11
Bit 2
SP10
R/W Address:
0F_hex + Base Address
R/W Address:
2F_hex + Base Address
Bit 1
Bit 0
SP9
SP8
Power-up
ECA: Sin Peak Detect Register 1 (SP)
R/W Address:
N/A
0E_hex + Base Address
ECB: Sin Peak Detect Register 1 (SP)
R/W Address:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
2E_hex + Base Address
Bit 1
Bit 0
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
Functional Description of Register Bits
These peak detector registers allow the user to monitor the send in (Sin) peak signal level. The information is in
16-bit 2’s complement linear coded format presented in two 8 bit registers for each echo canceller. The high
byte is in Register 2 and the low byte is in Register 1.
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Zarlink Semiconductor Inc.