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ZL38002 Datasheet, PDF (26/47 Pages) Zarlink Semiconductor Inc – Low-Voltage Acoustic Echo Canceller With Noise Reduction
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ZL38002
Data Sheet
Read/Write Page 0, Address: 12H
Reset Value: 00H
7
6
5
Reserved
Reserved
Reserved
4
Reserved
3
Reserved
2
Reserved
1
Reserved
0
SoutGR
Bit
7-1
0
Name
Description
Reserved
Reserved: Must be set to low
SoutGR
This bit will provide an automatic signal reduction on Sout by 12 dB (far-end
speaker) when double talk is present with this bit set to 1.
Register Table 9 - Sout Gain Reduction (SoutGR)
Read/Write Page 0, Address: 1DH
Reset Value: 08H
15
14
13
Reserved
Reserved
Reserved
12
Reserved
11
XRAMGain3
10
XRAMGain2
9
XRAMGain1
8
XRAMGain0
Read/Write Page 0, Address: 1CH
Reset Value: 88H
7
6
5
SoutGain3 SoutGain2 SoutGain1
4
SoutGain0
3
SinGain3
2
SinGain3
1
SinGain3
0
SinGain3
Bit
15-12
11-8
7-4
3-0
Name
Description
Reserved
XRAMGain3-0
SoutGain3-0
SinGain3-0
Reserved: Must be set to low
Gain control for ROUT to Xram, range from -24 dB to 21 dB. (1111=+21dB,
0000=-24 dB)
Gain control for SOUT, range from -24 dB to 21 dB. (1111=+21dB, 0000=-
24 dB)
Gain control for SIN, range from -24 dB to 21 dB. (1111=+21dB, 0000=-
24 dB)
Register Table 10 - Customer Gain Control Registers (CGCR1) & (CGCR2)
26
Zarlink Semiconductor Inc.
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