MT90866 Datasheet, PDF (23/86 Pages) Mitel Networks Corporation – WAN Access Switch

MT90866
Data Sheet
11.0 Address Mapping of Memories and Registers
The address bus on the microprocessor interface selects the internal registers and memories of the MT90866. If
the address bit A13 is low, then the registers are addressed by A12 to A0 as shown in Table 7 on page 23.
A13 - A0
Location
0000_H Control Register, CR
0001_H Device Mode Selection Register, DMS
0002_H Block Programming Mode Register, BPM
0003_H Reserved
0004_H Local Input Bit Delay Register 0, LIDR0
0005_H Local Input Bit Delay Register 0, LIDR1
0006_H Local Input Bit Delay Register 2, LIDR2
0007_H Local Input Bit Delay Register 3, LIDR3
0008_H Local Input Bit Delay Register 4, LIDR4
0009_H Local Input Bit Delay Register 5, LIDR5
000A_H Local Input Bit Delay Register 6, LIDR6
000B_H Local Input Bit Delay Register 7, LIDR7
000C_H Local Input Bit Delay Register 8, LIDR8
000D_H Local Input Bit Delay Register 9, LIDR9
000E_H Reserved
to 001B_H
001C_H Backplane Output Advancement Register 0, BOAR0
001D_H Backplane Output Advancement Register 1, BOAR1
001E_H Backplane Output Advancement Register 2, BOAR2
001F_H Backplane Output Advancement Register 3, BOAR3
0020_H Local Output Advancement Register 0, LOAR0
0021_H Local Output Advancement Register 1, LOAR1
0022_H Local Output Advancement Register 2, LOAR2
0023_H Local Output Advancement Register 3, LOAR3
0024_H Reserved
to 0026_H
0027_H Local BER Input Selection Register, LBIS
0028_H Local BER Register, LBERR
0029_H Backplane BER Input Selection Register, BBIS
002A_H Backplane BER Register, BBERR
002B_H DPLL Operation Mode Register 1, DOM1
Table 7 - Address Map For Internal Registers (A13 = 0)
23
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