ZL50010_06 Datasheet, PDF (22/87 Pages) Zarlink Semiconductor Inc – Flexible 512 Channel DX with Enhanced DPLL

ZL50010
Data Sheet
2.2.3 ST-BUS Output Timing
By default, the output frame boundary is defined by the falling edge of the CKo0, CKo1 or CKo2 output clock while
the FPo0, FPo1 or FPo2 output frame pulse goes low respectively. When the output data rates are 2.048 Mbps,
4.096 Mbps and 8.192 Mbps, there are 32, 64 or 128 output channels per every ST-BUS frame respectively. Figure
14 describes the details.
FPo0
(8 kHz)
CKo
(4.096 MHz)
FPo0 or FPo1
CKo0 or CKo1
(8.192 MHz)
FPo1 or FPo2
CKo1 or CKo2
(16.384 MHz)
FPo2
CKo2
(32.768 MHz)
Channel 0
STo
(2.048 Mbps)
0
7
6
5
4
STo
(4.096 Mbps)
Channel 0
107654 3210
STo
(8.192 Mbps)
Channel 0
Channel 1
321076543210 76543210
Channel 31
3
2
1
0
7
Channel 63
654 32107
Channel 126
Channel 127
6543210 7654321076
Output Frame Boundary
Output Frame Boundary
Figure 14 - ST-BUS Output Timing for Various Output Data Rates
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Zarlink Semiconductor Inc.