ZL38070_06 Datasheet, PDF (20/51 Pages) Zarlink Semiconductor Inc – 256 Channel Voice Echo Canceller

ZL38070
Data Sheet
In Back-to-Back configuration, writing a “1” into the MuteR bit of Echo Canceller A, Control Register 2, causes
quiet code to be transmitted on Rout. Writing a “1” into the MuteS bit of Echo Canceller A, Control Register 2,
causes quiet code to be transmitted on Sout.
In Extended Delay and in Back-to-Back configurations, MuteR and MuteS bits of Echo Canceller B must always be
“0”. Refer to Figure 4 and to Control Register 2 for bit description.
3.2 Bypass
The Bypass state directly transfers PCM codes from Rin to Rout and from Sin to Sout. When Bypass state is
selected, the Adaptive Filter coefficients are reset to zero. Bypass state must be selected for at least one frame
(125 µs) in order to properly clear the filter.
3.3 Disable Adaptation
When the Disable Adaptation state is selected, the Adaptive Filter coefficients are frozen at their current value. The
adaptation process is halted, however, the echo canceller continues to cancel echo.
3.4 Enable Adaptation
In Enable Adaptation state, the Adaptive Filter coefficients are continually updated. This allows the echo canceller
to model the echo return path characteristics in order to cancel echo. This is the normal operating state.
The echo canceller functions are selected in Control Register 1 and Control Register 2 through four control bits:
MuteS, MuteR, Bypass and AdaptDis. Refer to 8.0, “EVP Register Description“ on page 28 for details.
4.0 Echo Voice Processor (EVP) Throughput Delay
The throughput delay of the EVP varies according to the device configuration. For all device configurations, Rin to
Rout has a delay of two frames and Sin to Sout has a delay of three frames. In Bypass state, the Rin to Rout and
Sin to Sout paths have a delay of two frames.
5.0 Serial PCM I/O channels
There are four TDM I/O streams, each with channels numbered from 0 to 31. One input stream is for Receive (Rin)
channels, and the other input stream is for Send (Sin) channels. Likewise, two output streams is for Rout PCM
channels, and Sout PCM channels. See Figure 10 for channel allocation.
5.1 Serial Data Interface Timing
The ZL38070 provides ST-BUS and GCI interface timing. The Serial Interface clock frequency, C4i, is 4.096 MHz.
The input and output data rate of the ST-BUS and GCI bus is 2.048 Mb/s.
The 8 KHz input frame pulse can be in either ST-BUS or GCI format. The EVP automatically detects the presence
of an input frame pulse and identifies it as either ST-BUS or GCI. In ST-BUS format, every second falling edge of
the C4i clock marks a bit boundary, and the data is clocked in on the rising edge of C4i, three quarters of the way
into the bit cell (See Figure 14). In GCI format, every second rising edge of the C4i clock marks the bit boundary,
and data is clocked in on the second falling edge of C4i, half the way into the bit cell (see Figure 15).
20
Zarlink Semiconductor Inc.