ZL30415 Datasheet, PDF (20/23 Pages) Zarlink Semiconductor Inc – SONET/SDH Clock Multiplier PLL

ZL30415
Data Sheet
Performance Characteristics: Output Jitter Generation (LVPECL: 19.44 MHz, 38.88 MHz, 77.76 MHz,
155.52 MHz, and 622.08 MHz and CMOS: 19.44 MHz) - ETSI EN 300 462-7-1 conformance - (V_CC = 3.3 V ±10%; T_A
= -40 to 85°C)
EN 300 462-7-1 Jitter Generation Requirements
ZL30415 Jitter Generation Performance
Interface
Jitter
Measurement
Filter
Limit in
UI
Equivalent
limit in time
domain
1 STM-4
2 STM-1
optical
3 STM-1
electrical
250 kHz to 5 MHz
1 kHz to 5 MHz
65 kHz to 1.3 MHz
500 Hz to 1.3 MHz
65 kHz to 1.3 MHz
500 Hz to 1.3 MHz
0.1 UIpp
-
0.5 UIpp
-
0.1 UIpp
-
0.5 UIpp
-
0.075 UIpp
-
0.5 UIpp
-
161
-
804
-
643
-
3215
-
482
-
3215
-
† Typical figures are for design aid only: not guaranteed and not subject to production testing.
‡ Loop Filter components: R_F = 8.2 kΩ, C_F = 470 nF.
Typ.^†
1.5
4
1.6
5
1.6
5
Max.^‡
Units
30
ps_P-P
3
ps_RMS
80
ps_P-P
8
ps_RMS
31
ps_P-P
3.1
ps_RMS
100
ps_P-P
10
ps_RMS
31
ps_P-P
3.1
ps_RMS
100
ps_P-P
10
ps_RMS
20
Zarlink Semiconductor Inc.