MT9075B Datasheet, PDF(20/102 Page) Mitel Networks Corporation

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MT9075B Datasheet, PDF (20/102 Pages) Mitel Networks Corporation – E1 Single Chip Transceiver

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MT9075B

Data Sheet

Add

ress

Frames 1, 3, 5, 7, 9, 11, 13 & 15 of a CRC-4

Multiframe

able

Byte

Sa4 Sa4 Sa4 Sa4 Sa4 Sa4 Sa4 Sa4

Sa5 Sa5 Sa5 Sa5 Sa5 Sa5 Sa5 Sa5

Sa6 Sa6 Sa6 Sa6 Sa6 Sa6 Sa6 Sa6

Sa7 Sa7 Sa7 Sa7 Sa7 Sa7 Sa7 Sa7

Sa8 Sa8 Sa8 Sa8 Sa8 Sa8 Sa8 Sa8

Table 8 - MT9075B National Bit Buffers

Note that the Data Link (DL) pin functions, if selected, override the transmit national bit buffer function.

The CRC-4 Alignment status CALN (page 03H, address 12H) and maskable interrupt CALNI (page 01H, address

1DH) indicate the beginning of every received CRC-4 multiframe.

Maskable interrupts are available for change of state of Sa5 bits or change of state of Sa6 nibbles. By writing the

proper control bits, an interrupt can be generated on a change of state of any Sa bit (except Sa4 - normally reserved

for the data link), or any nibbles for Sa5 through Sa8. See the description of page 01H, address 19H for more details.

In addition, the transparent transmission of channel 0 is supported to meet the ETS requirement. Selectable on a bit

by bit basis, Sa bits in channel 0 DSTi data can be programmed using register 17H of page 01H to be sent

transparently onto the line.

Data Link Operation

Timeslot 0

The MT9075B has a user defined 4, 8, 12, 16 or 20 kbit/s data link for transport of maintenance and performance

monitoring information across the PCM 30 link. This channel functions using the Sa bits (Sa4~Sa8) of the PCM 30

timeslot zero non-frame alignment signal (NFAS). Since the NFAS is transmitted every other frame - a periodicity of

250 microseconds - the aggregate bit rate is a multiple of 4 kb/s. As there are five Sa bits independently available

for this data link, the bit rate will be 4, 8, 12, 16 or 20 kb/s, depending on the bits selected for the Data Link (DL).

The Sa bits used for the DL are selected by setting the appropriate bits, Sa4~Sa8, to one in the Data Link Select

Word (page 01H, address 10H, bits 4-0). Access to the DL is provided by pins TxDLCLK, TxDL, RxDLCLK and

RxDL, which allow easy interfacing to an external controller.

Data to be transmit onto the line in the Sa bit position is clocked in from the TxDL pad (pin 65 in PLCC, pin 62 in

MQFP) with the clock TxDLCLK (pin 64 in PLCC, pin 61 in MQFP). Although the aggregate clock rate equals the bit

rate, it has a nominal pulse width of 244 ns, and it clocks in the TxDL as if it were a 2.048 Mb/s data stream. The

clock can only be active during bit times 4 to 0 of the STBUS frame. The TxDL input signal is clocked into the

MT9075B by the rising edge of TxDLCLK. If bits are selected to be a part of the DL, all other programmed functions

for those Sa bit positions are overridden.

The RxDLCLK signal (pin 39 in PLCC, pin 20 in MQFP) is derived from the receive extracted clock and is

aligned with the receive data link output RxDL. The HDB3 decoded receive data, at 2.048 Mbit/s, is clocked out

Zarlink Semiconductor Inc.

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