MT3171B Datasheet, PDF (2/15 Pages) Zarlink Semiconductor Inc – Wide Dynamic Range DTMF Receiver

MT3170B/71B, MT3270B/71B, MT3370B/71B
Data Sheet
Description
The MT3x7xB is a family of high performance DTMF receivers which decode all 16 tone pairs into a 4-bit binary
code. These devices incorporate an AGC for wide dynamic range and are suitable for end-to-end signalling. The
MT3x70B provides an early steering (ESt) logic output to indicate the detection of a DTMF signal and requires
external software guard time to validate the DTMF digit. The MT3x71B, with preset internal guard times, uses a
delay steering (DStD) logic output to indicate the detection of a valid DTMF digit. The 4-bit DTMF binary digit can be
clocked out synchronously at the serial data (SD) output. The SD pin is multiplexed with call progress detector
output. In the presence of supervisory tones, the call progress detector circuit indicates the cadence (i.e., envelope)
of the tone burst. The cadence information can then be processed by an external microcontroller to identify specific
call progress signals. The MT327xB and MT337xB can be used with a crystal or a ceramic resonator without
additional components. A power-down option is provided for the MT317xB and MT337xB.
MT3170B/71B
MT3270B/71B
INPUT ₁
PWDN 2
CLK 3
VSS 4
8 ^{VDD INPUT} 1
7
ESt/
DStD
OSC2
2
6 ACK OSC1 3
5 SD
VSS 4
8 ^VDD
7
ESt/
DStD
6 ACK
5 SD
8 PIN PLASTIC DIP
MT3370B/71B
NC 1
INPUT ²
PWDN 3
OSC2 4
NC 5
OSC1 6
NC 7
NC 8
VSS 9
18 _VDD
17 NC
16 NC
15 ESt/DStD
14 NC
13 ACK
12 NC
11 SD
10 NC
18 PIN PLASTIC SOIC
NC
NC
INPUT
PWDN
NC
OSC2
OSC1
VSS
NC
NC
MT3370B/71B
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
20 PIN SSOP
NC
NC
VDD
NC
ESt/DStD
NC
ACK
SD
NC
NC
Pin Description
337xB
2
4
6
Pin #
327xB
1
2
3
9
4
11
5
13
6
317xB
1
-
3
4
5
6
Figure 2 - Pin Connections
Name
Description
INPUT
OSC2
OSC1
(CLK)
V_SS
SD
ACK
DTMF/CP Input. Input signal must be AC coupled via capacitor.
Oscillator Output.
Oscillator/Clock Input. This pin can either be driven by:
1) an external digital clock with defined input logic levels. OSC2
should be left open.
2) connecting a crystal or ceramic resonator between OSC1 and
OSC2 pins.
Ground. (0V)
Serial Data/Call Progress Output. This pin serves the dual function
of being the serial data output when clock pulses are applied after
validation of DTMF signal, and also indicates the cadence of call
progress input. As DTMF signal lies in the same frequency band as
call progress signal, this pin may toggle for DTMF input. The SD pin
is at logic low in powerdown state.
Acknowledge Pulse Input. After ESt or DStD is high, applying a
sequence of four pulses on this pin will then shift out four bits on the
SD pin, representing the decoded DTMF digit. The rising edge of the
first clock is used to latch the 4-bit data prior to shifting. This pin is
pulled down internally. The idle state of the ACK signal should be
low.
2
Zarlink Semiconductor Inc.