 English |
|
|
|
|
|
|
|
| MVTX2804 Datasheet, PDF (162/174 Pages) Zarlink Semiconductor Inc – 8-Port 1000 Mbps Ethernet Distributed Switch | |||
| |||
| ◁ |
MVTX2804
12.5.3 Typical CPU Timing Diagram for a CPU Read Cycle
Data Sheet
P_ADDR
P_CS#
P_RD#
DATA to CPU
ADDR0
ADDR1
TRS
TRA
TRH
at least
TRS
2 SCLKs
TRR
Recovery Time
at least 3 SCLKs
TDV
Valid time
DATA 0
TDI
2ns
Inactive time
TRA
TRH
at least
2 SCLKs
DATA 1
TDV
TDI
Figure 10 - Typical CPU Timing Diagram for a CPU Read Cycle
Description
(SCLK=133Mhz)
Read Cycle
Read Set up Time
Read Active Time
Read Hold Time
Read Recovery time
Data Valid time
Data Inactive time
Symbol Min (ns) Max (ns)
TRS
10
TRA
15
TRH
2
TRR
22.5
TDS
10
TDI
2
Table 7 - CPU Read Cycle
At least 2 SCLK
At least 3 SCLK
162
Zarlink Semiconductor Inc.
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese