MT90820 Datasheet, PDF (16/37 Pages) Mitel Networks Corporation – CMOS ST-BUS™ FAMILY Large Digital Switch (LDX)

MT90820
Data Sheet
Read Address:
Reset Value:
02_H,
0000_H.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
0
0 CFE FD11 FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0
Bit
10 - 0
Name
FD10-0
Description
Frame Delay Bits. The binary value expressed in these bits refers to the measured
input offset value. These bits are reset to zero when the SFE bit of the IMS register
changes from 1 to 0. (FD10 = MSB, FD0 = LSB)
Table 10 - Frame Alignment (FAR) Register Bits
ST-BUS Frame
CLK
Offset Value
FE Input
GCI Frame
CLK
Offset Value
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
(FD[10:0] = 06_H)
(FD11 = 0, sample at CLK low phase)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FE Input
(FD[10:0] = 09_H)
(FD11 = 1, sample at CLK high phase)
Figure 3 - Example for Frame Alignment Measurement
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