ZL50012_06 Datasheet, PDF (13/66 Pages) Zarlink Semiconductor Inc – Flexible 512-ch Digital Switch

ZL50012
Data Sheet
1.0 Device Overview
The device uses the ST-BUS input frame pulse and the ST-BUS input clock to define the input frame boundary and
timing for the ST-BUS input streams with various data rates (2.048 Mb/s, 4.096 Mb/s and/or 8.192 Mb/s). The
output frame boundary is defined by the output frame pulses and the output clock timing for the ST-BUS output
streams with various data rates (2.048 Mb/s, 4.096 Mb/s and/or 8.192 Mb/s).
By using Zarlink’s message mode capability, microprocessor data can be broadcast to the data output streams on a
per channel basis. This feature is useful for transferring control and status information for external circuits or other
ST-BUS devices.
A non-multiplexed microprocessor port allows users to program the device with various operating modes and
switching configurations. Users can use the microprocessor port to perform register read/write, connection memory
read/write and data memory read operations. The microprocessor port has a 12-bit address bus, a 16-bit data bus
and four control signals.
The device also supports the mandatory requirements of the IEEE-1149.1 (JTAG) standard via the test port.
2.0 Functional Description
A functional block diagram of the ZL50012 is shown in Figure 1 on page 1.
2.1 ST-BUS Input Data Rate and Input Timing
The device has sixteen ST-BUS serial data inputs. Any of the sixteen inputs can be programmed to accept different
data rates, 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s.
2.1.1 ST-BUS Input Operation Mode
Any ST-BUS input can be programmed to accept the 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s data using Bit 0 to 2 in
the stream input control registers, SICR0 to SICR15 as shown in Table 20 on page 42 and Table 21 on page 44.
The maximum number of input channels is 512 channels. External pull-up or pull-down resistors are required for
any unused ST-BUS inputs.
2.1.2 Frame Pulse Input and Clock Input timing
The frame pulse input FPi accepts the frame pulse used for the highest input data rate. The frame pulse is an
8 kHz input signal which stays low for 244 ns, 122 ns or 61 ns for the input data rate of 2.048 Mb/s, 4.096 Mb/s or
8.192 Mb/s respectively. The frequency of CKi must be twice the highest data rate. For example, if users present
the ZL50012 with 2.048 Mb/s and 8.192 Mb/s input data, the device should be programmed to accept the input
clock of 16.384 MHz and the frame pulse which stays low for 61 ns.
Users have to program the CKIN2 - 0 bits in the Control Register (CR), for the width of the frame pulse low cycle
and the frequency of the input clock. See Table 1 for the programming of the CKIN0, CKIN1 and CKIN2 bits in the
Control Register.
CKIN2 - 0 bits
000
001
010
011 - 111
FPi Low Cycle
CKi
61 ns
122 ns
244 ns
16.384 MHz
8.192 MHz
4.096 MHz
Reserved
Highest Input Data Rate
8.192 Mb/s
4.096 Mb/s
2.048 Mb/s
Table 1 - FPi and CKi Input Programming
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Zarlink Semiconductor Inc.