MT933 Datasheet, PDF (13/20 Pages) Zarlink Semiconductor Inc – 3.3V 10/100 Fast Ethernet Transceiver to MII

MT933
reg 21 - MII interrupt control register
Bit
21.15:0
Bit name Description
Clear Interrupt Write any data pattern to clear MINT
reg 22, 23 - Test registers
Bit
Bit name Description
15:0
reserved test mode only
Default
R/W
0
WO
Default
R/W
0000
res
reg 24- MT933 specific register
Bit
Bit name Description
Default
R/W
24.15:14 PWRCON[1:0] Low power controls:
00
RW
00 = full receive path active. No transmit.
01 = Deep sleep (all off including VREF & OSC)
10 = Sleep (generate MII interrupt on activity)
11 = auto shut down, auto wake on activity
24.13
MINTPOL
1 = MINT output active high
0 = MINT output active low
0
RW
24.12
Pol Dis
1 = disable 10Base-T autopolarity correction
0
RW
24.11
SQE disable 1 = disable SQE in 10Base-T half duplex mode
0
RW
24.10
JAB disable
0 = in case of jabber the 10Base-T will cut the
transmitted frame (normal operation)
1 = Jabber function disable
0
RW
24. 9
loop 10
1 = enable MII loopback in 10Base-T half duplex mode 0
RW
24.8
Force RX Force receive regardless of link
0
RW
24.7
Force TX Force transmit regardless of link
0
RW
24.6
CRS_CTL CRS behavior in full duplex mode:-
0 = CRS is active for transmit only
1= CRS active for receive or transmit
0
RW
24.5
MF
1 = MDIO data accepted without preamble
0
RW
24.4
Byp ALIGN 0 = normal operation
1 = bypass the aligner function
0
RW
24.3
Byp ENC 0 = normal operation
1 = bypass the 4B5B encoder function
0
RW
24.2
Byp SCR 0 = normal operation
1 = bypass the scrambler function
0
RW
24.1
DISCEN
0 = disable disconnection events
0
RW
1 = enable disconnect on false carrier detection
24:0
RPTR
Set repeater mode (affects CRS generation)
0
RW
12