MT88E45 Datasheet, PDF (12/30 Pages) Mitel Networks Corporation – 4-Wire Calling Number Identification Circuit 2(4-Wire CNIC2)

MT88E45
Data Sheet
For 3 V operation, the FSK receiver becomes more sensitive and lower level signals will be accepted than at 5 V. To
maintain the FSK reject level, the Tip/Ring input op-amp gain should be reduced. Note that since the Tip/Ring op-
amp is also used for Tip/Ring CAS detection, the CAS level will also be reduced for on-hook detection.
FSK Data Interface
The MT88E45B provides a powerful dual mode 3-wire interface so that the data bytes in the demodulated FSK bit
stream can be extracted without the need either for an external UART or for the CPE’s microcontroller to perform
the function in software. The interface is specifically designed for the 1200 baud rate and is consisted of 3 pins:
DATA, DCLK (Data Clock) and DR (Data Ready). DR/STD is a dual purpose output pin. When FSK is selected it is
DR.
Two modes (modes 0 and 1) are selectable via the CB0 pin. In mode 0, the FSK bit stream is output directly. In
mode 1, the data byte and the trailing stop bit are stored in a 9 bit buffer. If mode 1 is desired, the CB0 pin can be
hardwired to Vdd. If mode 0 is desired and full chip power down is not required, the CB0 pin can be hardwired to
Vss.
In Bellcore’s off-hook protocol, a Type 2 CPE should restore the voicepath within 50 ms after the end of the FSK
signal. Due to noise, end of carrier detection is not always reliable. The TIA Type 2 standard stipulates that the CPE
must detect the end of FSK when any one of the following occurs:
• absence of carrier signal or,
• more than five framing errors (trailing stop bit a 0 instead of a 1) have been detected in the FSK message or,
• more than 150 ms of continuous mark signal or space signal has been detected.
Mode 0 - Bit Stream Mode
This mode is selected when the CB0 pin is low. In this mode the FSK data is output directly to the DATA pin. DCLK
and DR pins are timing signal outputs (see Figure 13.
For each received stop and start bit sequence, the MT88E45B outputs a fixed frequency clock string of 8 pulses at
the DCLK pin. Each DCLK rising edge occurs in the middle of a DATA bit cell. DCLK is not generated for the start
and stop bits. Consequently, DCLK will clock only valid data into a peripheral device such as a serial to parallel shift
register or a microcontroller. The MT88E45B also outputs an end of word pulse (Data Ready) at the DR pin. DR
goes low for half a nominal bit time at the beginning of the trailing stop bit. It can be used to interrupt a
microcontroller or cause a serial to parallel converter to parallel load its data into the microcontroller. Since the DR
rising edge occurs in the middle of the stop bit, it can also be used to read the stop bit to check for framing error.
Alternatively, DCLK and DATA may occupy 2 bits of a microcontroller’s input port. The microcontroller polls the
input port and saves the DATA bit whenever DCLK changes from low to high. When DR goes low, the word may
then be assembled from the last 8 saved bits.
DATA may also be connected to a personal computer’s serial communication port after conversion from CMOS to
RS-232 voltage levels.
Mode 1 - Buffer Mode
This mode is selected when the CB0 pin is high. In this mode the received byte is stored on chip. At the end of a
byte DR goes low to indicate that a new byte has become available. The microcontroller applies DCLK pulses to
read the register contents serially out of the DATA pin (see Figure 1414).
Internal to the MT88E45B, the start bit is stripped off, the data bits and the trailing stop bit are sampled and stored.
Midway through the stop bit, the 8 data bits and the stop bit are parallel loaded into a 9 bit shift register and DR
goes low. The register’s contents are shifted out to the DATA pin on the supplied DCLK’s rising edges in the order
they were received. The last bit must be shifted out and DCLK returned to low before the next DR. DCLK must be
low for t_DDS before DR goes low and must remain low for t_DDH after DR has gone low (see Figure 14).
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Zarlink Semiconductor Inc.