MT8941 Datasheet, PDF (11/27 Pages) Mitel Networks Corporation – CMOS ST-BUS™ FAMILY Advanced T1/CEPT Digital Trunk PLL

MT8941B
Data Sheet
Figure 6 - The Jitter Transfer Function for PLL1
Figure 7 - The Jitter Transfer Function for PLL2
However, if DPLL #1 and DPLL #2 are daisy-chained as shown in Figures 9 and 10, the output clock tolerance of
DPLL #1 will be equal to that of the DPLL #2 oscillator when DPLL #2 is free-running. In this case, the oscillator
tolerance of DPLL #1 has no impact on its output clock tolerance. For this reason, it is recommended to use a
±32 ppm oscillator for DPLL #2 and a ±100 ppm oscillator for DPLL #1.
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