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ZL50407 Datasheet, PDF (1/125 Pages) Zarlink Semiconductor Inc – Lightly Managed/Unmanaged 8-Port 10/100M + 1-Port 10/100/1000M Ethernet Switch | |||
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Features
⢠Integrated Single-Chip 10/100/1000 Ethernet
Switch
⢠Eight 10/100 Mbps auto-negotiating Fast
Ethernet (FE) ports with RMII, MII, GPSI,
Reverse MII & Reverse GPSI interface options
⢠One 10/100/1000 Mbps auto-negotiating port
with GMII & MII interface options, that can be
used as a WAN uplink or as a 9th port
⢠Operates stand-alone or can be cascaded with a
second ZL50407 to reach 16 ports
⢠Embedded 2 Mbits (256 KBytes) internal memory
⢠supports up to 4 K byte frames
⢠L2 switching
⢠MAC address self learning, up to 4 K MAC
addresses using internal table
⢠Supports the following spanning standards
- IEEE 802.1D spanning tree
- IEEE 802.1w rapid spanning tree
⢠Supports Ethernet multicasting and
broadcasting and flooding control
⢠VLAN Support
⢠Supports port-based VLAN
ZL50407
Lightly Managed/Unmanaged
8-Port 10/100M +
1-Port 10/100/1000M Ethernet Switch
Data Sheet
August 2004
Ordering Information
ZL50407GDC
208 Pin LBGÎ
-40°C to +85°C
⢠CPU access supports the following interface
options:
⢠Serial interface in lightly managed mode, or in
unmanaged mode with optional I2C EEPROM
interface
⢠Failover Features
⢠Rapid link failure detection using
hardware-generated heartbeat packets
⢠link failover in less than 50 ms
⢠Rate Control (both ingress and egress)
⢠Bandwidth rationing, Bandwidth on demand,
SLA (Service Level Agreement)
⢠Smooth out traffic to uplink port
⢠Ingress Rate Control
- Back pressure
- Flow Control
- WRED (Weighted Random Early Discard)
C
P
Serial
U
ZL50407
GMII / MII
8-Port 10/100M + 1G
Ethernet Switch
EEPROM I2C
10/100/
1000
PHY
RMII / MII / GPSI
Quad
10/100
PHY
Quad
10/100
PHY
Figure 1 - System Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved.
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