ZL50405 Datasheet, PDF (1/132 Pages) Zarlink Semiconductor Inc – Managed5-Port 10/100 M Ethernet Switch

ZL50405
Managed5-Port 10/100 M Ethernet Switch
Data Sheet
Features
• Integrated Single-Chip 10/100 Ethernet Switch
• Four 10/100 Mbps auto-negotiating Fast
Ethernet (FE) ports with RMII, MII, GPSI,
Reverse MII & Reverse GPSI interface options
• One 10/100 Mbps auto-negotiating port with
MII interface option, that can be used as a
WAN uplink or as a 9th port
• a 10/100 Mbps Fast Ethernet (FE) CPU port
with Reverse MII interface option
• Embedded 2 Mbits (256 KBytes) internal memory
• supports up to 4 K byte frames
• L2 switching
• MAC address self learning, up to 4 K MAC
addresses using internal table
• Supports IP Multicast with IGMP snooping, up
to 4 K IP Multicast groups
• Supports the following spanning standards
- IEEE 802.1D spanning tree
- IEEE 802.1w rapid spanning tree
• Supports Ethernet multicasting and
broadcasting and flooding control
• VLAN Support
• Supports port-based VLAN and tagged-based
January 2005
Ordering Information
ZL50405GDC
208 Pin LBGA
-40°C to +85°C
VLAN (IEEE 802.1Q), up to 4 K VLANs
• Supports both shared VLAN learning (SVL)
and independent VLAN learning (IVL)
• CPU access supports the following interface
options:
• 8/16-bit parallel and Serial+MII interface in
managed mode
• Serial interface in lightly managed mode, or in
unmanaged mode with optional I²C EEPROM
interface
• Failover Features
• Rapid link failure detection using
hardware-generated heartbeat packets
• link failover in less than 50 ms
• Rate Control (both ingress and egress)
• Bandwidth rationing, Bandwidth on demand,
8/16-bit
or
C
Serial
P
U
MII
I²C
EEPROM
ZL50405
MII
5-Port 10/100M
Ethernet Switch
RMII / MII / GPSI
10/100
PHY
Quad
10/100
PHY
Figure 1 - System Block Diagram
1
Zarlink Semiconductor Inc.
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Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.