ZL50235 Datasheet, PDF (1/39 Pages) Zarlink Semiconductor Inc – 16 Channel Voice Echo Canceller

ZL50235
16 Channel Voice Echo Canceller
Data Sheet
Features
• Independent multiple channels of echo
cancellation; from 16 channels of 64ms to 8
channels of 128ms with the ability to mix
channels at 128ms or 64ms in any combination
• Independent Power Down mode for each group of
2 channels for power management
• Fully compliant to ITU-T G.165, G.168 (2000) and
(2002) specifications
• Passed AT&T voice quality testing for carrier
grade echo cancellers.
• Compatible to ST-BUS and GCI interfaces with
2Mb/s serial PCM data
• PCM coding, µ/A-Law ITU-T G.711 or sign
magnitude
• Per channel Fax/Modem G.164 2100Hz or G.165
2100Hz phase reversal Tone Disable
• Per channel echo canceller parameters control
• Transparent data transfer and mute
• Fast reconvergence on echo path changes
• Fully programmable convergence speeds
• Patented Advanced Non-Linear Processor with
high quality subjective performance
• Protection against narrow band signal divergence
and instability in high echo environments
• 0 dB to -12 dB level adjusters (3 dB steps) at all
signal ports
March 2003
Ordering Information
ZL50235/QCC 100-Pin LQFP
ZL50235/GDC 208-Ball LBGA
-40°C to +85°C
• Offset nulling of all PCM channels
• 10 MHz or 20 MHz master clock operation
• 3.3 V IO pads and 1.8V Logic core operation with
5-Volt tolerant inputs
• IEEE-1149.1 (JTAG) Test Access Port
• ZL50232, ZL50233, ZL50234 and ZL50235 have
same pinouts in both LQFP and LBGA packages
Applications
• Voice over IP network gateways
• Voice over ATM, Frame Relay
• T1/E1/J1 multichannel echo cancellation
• Wireless base stations
• Echo Canceller pools
• DCME, satellite and multiplexer system
Rin
Sin
MCLK
Fsel
C4i
F0i
V_{DD1 (3.3V)}
V_SS
V_{DD2 (1.8V)}
ODE
Serial
to
Parallel
PLL
Timing
Unit
Echo Canceller Pool
Group 0 Group 1 Group 2
ECA/ECB ECA/ECB ECA/ECB
Group 4 Group 5 Group 6
ECA/ECB ECA/ECB ECA/ECB
Group 3
ECA/ECB
Group 7
ECA/ECB
Parallel
to
Serial
Note:
Refer to Figure 4
for Echo Canceller
block diagram
Microprocessor Interface
Test Port
Rout
Sout
RESET
DS CS R/W A10-A0 DTA D7-D0 IRQ TMS TDI TDO TCK TRST
Figure 1 - ZL50235 Device Overview
1