ZL50130 Datasheet, PDF (1/60 Pages) Zarlink Semiconductor Inc – Ethernet Pseudo-Wires across a PSN

ZL50130
Ethernet Pseudo-Wires across a PSN
Data Sheet
Applications
• Ethernet Pseudo-Wires across a Packet Switch
Network
Features
Ethernet Pseudo-Wire Emulation Functions
Supports the following functions for Ethernet Pseudo-
Wire emulation over the packet domain:
• Transports the complete Ethernet frame (less
preamble and FCS) across the PSN
• Supports up to 127 point-to-point pseudo-wire
links across the PSN
• VLAN priority field may be used to determine
class of service on the PSN
• complies with the standards for Ethernet pseudo-
wires proposed in the IETF’s PWE3 working
group
Network Interfaces
• 3 x 100 Mbit/s MII interfaces
October 2004
Ordering Information
ZL50130 PBGA
-40^°C to +85^°C
System Interfaces
• Flexible 32-bit host CPU interface (Motorola
PowerQUICC™ II compatible)
• Dual address DMA transfer of packets to or from
the CPU
• On-chip packet memory for self-contained
operation
Packet Processing Functions
• Flexible, multi-protocol packet encapsulation, with
support for IPv4/6, MPLS, L2TP, PWE3
• Wire speed processing and forwarding of packets
• Packet sequencing and re-ordering where
required
• Four classes of service with programmable
priority mechanisms (WFQ and SP)
• Flexible classification of incoming packets at
layers 2, 3, 4 and 5
Host Processor Interface
Motorola PowerQUICC^TM II compatible
MAC
Host Processor Interface
with DMA support
packet
receive/classifier
protocol
engine
task
manager
packet transmit
- add layer 2/3 headers
memory management /
on-chip packet memory
MAC
Optional Off-chip Packet Memory
0-8 MBytes SSRAM
Figure 1 - High Level Overview
1
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Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved.