ZL50110_08 Datasheet, PDF (1/112 Pages) Zarlink Semiconductor Inc – 128, 256, 512 and 1024 Channel CESoP Processors

ZL50110/11/12/14
128, 256, 512 and 1024 Channel CESoP
Processors
Data Sheet
Features
General
• Circuit Emulation Services over Packet (CESoP)
transport for MPLS, IP and Ethernet networks
• On chip timing & synchronization recovery across
a packet network
• Grooming capability for Nx64 Kbps trunking
Circuit Emulation Services
• Supports ITU-T Recommendation Y.1413 and
Y.1453
• Supports IETF RFC4553 and RFC5086
• Supports MEF8 and MFA 8.0.0
• Structured, synchronous CESoP with clock
recovery
• Unstructured, asynchronous CESoP, with integral
per stream clock recovery
TDM Interfaces
• Up to 32 T1/E1, 8 J2, or 2 T3/E3 ports
• H.110, H-MVIP, ST-BUS backplanes
• Up to 1024 bi-directional 64 Kbps channels
April 2008
Ordering Information
ZL50110GAG
ZL50111GAG
ZL50112GAG
ZL50114GAG
ZL50110GAG2
ZL50111GAG2
ZL50112GAG2
ZL50114GAG2
552 PBGA
552 PBGA
552 PBGA
552 PBGA
552 PBGA**
552 PBGA**
552 PBGA**
552 PBGA**
Trays, Bake & Drypack
Trays, Bake & Drypack
Trays, Bake & Drypack
Trays, Bake & Drypack
Trays, Bake & Drypack
Trays, Bake & Drypack
Trays, Bake & Drypack
Trays, Bake & Drypack
**Pb Fee Tin Silver/Copper
-40°C to +85°C
• Direct connection to LIUs, framers, backplanes
• Dual reference Stratum 4 and 4E DPLL for
synchronous operation
Network Interfaces
• Up to 3 x 100 Mbps MII Fast Ethernet or Dual
Redundant 1000 Mbps GMII/TBI Ethernet
Interfaces
System Interfaces
• Flexible 32 bit host CPU interface (Motorola
PowerQUICC^™ compatible)
• On-chip packet memory for self-contained
operation, with buffer depths of over 16 ms
• Up to 8 Mbytes of off-chip packet memory,
supporting buffer depths of over 128 ms
TDM
Interface
(LIU , Fram er, Backplane)
Per Port DCO for
C lock R ecovery
M ulti-Protocol
Packet
P ro c e s s in g
E n g in e
PW , RTP, UDP,
IPv4, IPv6, MPLS,
ECID, VLAN, User
D efined, O thers
T rip le
Packet
Interface
MAC
(M II, G M II, TBI)
O n C hip Packet M em ory
(Jitter Buffer Com pensation for 16-128 m s of Packet D elay Variation)
Dual Reference
Stratum 3 D PLL
Host Processor
In te rfa c e
External M em ory
Interface (optional)
32-bit M otorola com patible
D M A for signaling packets
Z B T -S R A M
(0 - 8 Mbytes)
Figure 1 - ZL50111 High Level Overview
1
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Copyright 2003-2008, Zarlink Semiconductor Inc. All Rights Reserved.