ZL50075 Datasheet, PDF (1/60 Pages) Zarlink Semiconductor Inc – 32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 2 Streams (8, 16, 32 or 64 Mbps), and 64 Inputs and 64 Outputs

ZL50075
32 K Channel Digital Switch with High Jitter
Tolerance, Rate Conversion per Group of
2 Streams (8, 16, 32 or 64 Mbps),
and 64 Inputs and 64 Outputs
Data Sheet
Features
January 2006
• 32,768 channel x 32,768 channel non-blocking
digital Time Division Multiplex (TDM) switch at
65.536 Mbps or 32.768 Mbps or using a
combination of rates
• 16,384 channel x 16,384 channel non-blocking
digital TDM switch at 16.384 Mbps
• 8,192 channel x 8,192 channel non-blocking
digital TDM switch at 8.192 Mbps
• High jitter tolerance with multiple input clock
sources and frequencies
• Up to 64 serial TDM input streams, divided into
32 groups with 2 input streams per group
• Up to 64 serial TDM output streams, divided into
32 groups with 2 output streams per group
• Per-group input and output data rate conversion
selection at 65.536 Mbps, 32.768 Mbps,
16.384 Mbps and 8.192 Mbps. Input and output
data group rates can differ
• Per-group input bit delay for flexible sampling
point selection
• Per-group output fractional bit advancement
• Two sets of output timing signals for interfacing
additional devices
Ordering Information
ZL50075GAC 324 Ball PBGA Trays
ZL50075GAG2 324 Ball PBGA** Trays
**Pb Free Tin/Silver/Copper
-40°C to +85°C
• Per-channel A-Law/µ-Law Translation
• Per-channel constant or variable throughput delay
for frame integrity and low latency applications
• Per-stream Bit Error Rate (BER) test circuits
• Per-channel high impedance output control
• Per-channel force high output control
• Per-channel message mode
• Control interface compatible with Intel and
Motorola 16 bit non-multiplexed buses
• Connection memory block programming
• Supports ST-BUS and GCI-Bus standards for
input and output timing
• IEEE 1149.1 (JTAG) test port
• 3.3 V I/O with 5V tolerant inputs; 1.8 V core
voltage
STiA0
STiB0
:
:
STiA31
STiB31
FPi0
CKi0
CK_SEL1-0
FPo1-0
CKo1-0
VDD_CORE VDD_IO VSS
ODE PWR
S/P
Converter
Input
Timing
Data Memory
P/S
Converter
Connection Memory
Output
Timing
Timing
Microprocessor Interface
and Control Registers
Test Access
Port
SToA0
SToB0
:
:
SToA31
SToB31
Figure 1 - ZL50075 Functional Block Diagram
1
Zarlink Semiconductor Inc.
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Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved.