ZL50023 Datasheet, PDF (1/80 Pages) Zarlink Semiconductor Inc – Enhanced 4 K Digital Switch

ZL50023
Enhanced 4 K Digital Switch
Data Sheet
Features
• 4096 channel x 4096 channel non-blocking digital
Time Division Multiplex (TDM) switch at
8.192 Mbps and 16.384 Mbps or using a
combination of ports running at 2.048 Mbps,
4.096 Mbps, 8.192 Mbps and 16.384 Mbps
• 32 serial TDM input, 32 serial TDM output
streams
• Output streams can be configured as bi-
directional for connection to backplanes
• Exceptional input clock cycle to cycle variation
tolerance (20 ns for all rates)
• Per-stream input and output data rate conversion
selection at 2.048 Mbps, 4.096 Mbps 8.192 Mbps
or 16.384 Mbps. Input and output data rates can
differ
• Per-stream high impedance control outputs
(STOHZ) for 16 output streams
• Per-stream input bit delay with flexible sampling
point selection
October 2004
Ordering Information
ZL50023GAC 256-ball PBGA
ZL50023QCC 256-lead LQFP
-40°C to +85°C
• Per-stream output bit and fractional bit
advancement
• Per-channel ITU-T G.711 PCM A-Law/µ-Law
Translation
• Four frame pulse and four reference clock outputs
• Three programmable delayed frame pulse outputs
• Input clock: 4.096 MHz, 8.192 MHz, 16.384 MHz
• Input frame pulses: 61 ns, 122 ns, 244 ns
• Per-channel constant or variable throughput delay
for frame integrity and low latency applications
STi[31:0]
FPi
CKi
MODE_4M0
MODE_4M1
V_{DD_CORE}
V_{DD_IO}
V_{DD_COREA} V_{DD_IOA}
V_SS
RESET
ODE
S/P Converter
Data Memory
P/S Converter
Input Timing
Connection Memory
Output HiZ
Control
Output Timing
STio[31:0]
STOHZ[15:0]
FPo[3:0]
CKo[3:0]
FPo_OFF[2:0]
Internal Registers &
Microprocessor Interface
Test Port
Figure 1 - ZL50023 Functional Block Diagram
1
Zarlink Semiconductor Inc.
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Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved.